From 9dcfd5c314fe76fe558f54a3976aa61207f3bbcb Mon Sep 17 00:00:00 2001 From: David Garske Date: Fri, 10 Jul 2026 17:30:27 -0700 Subject: [PATCH 1/2] cm4: add Raspberry Pi Compute Module 4 (BCM2711 Cortex-A72) target with authenticated boot --- Makefile | 4 + arch.mk | 12 +- config/examples/cm4.config | 18 ++ config/examples/cm4_sdcard.config | 39 ++++ docs/Targets.md | 74 +++++++ hal/cm4.c | 314 ++++++++++++++++++++++++++++++ hal/cm4.h | 88 +++++++++ hal/cm4.ld | 71 +++++++ src/boot_aarch64_start.S | 4 + test-app/app_cm4.c | 128 ++++++++++++ 10 files changed, 751 insertions(+), 1 deletion(-) create mode 100644 config/examples/cm4.config create mode 100644 config/examples/cm4_sdcard.config create mode 100644 hal/cm4.c create mode 100644 hal/cm4.h create mode 100644 hal/cm4.ld create mode 100644 test-app/app_cm4.c diff --git a/Makefile b/Makefile index a011889aac..367487a27a 100644 --- a/Makefile +++ b/Makefile @@ -310,6 +310,10 @@ ifeq ($(TARGET),raspi3) MAIN_TARGET:=wolfboot.bin endif +ifeq ($(TARGET),cm4) + MAIN_TARGET:=wolfboot.bin +endif + ifeq ($(TARGET),sim) CFLAGS+=-fno-pie LDFLAGS+=-no-pie diff --git a/arch.mk b/arch.mk index a507f73226..91758e3265 100644 --- a/arch.mk +++ b/arch.mk @@ -169,8 +169,18 @@ ifeq ($(ARCH),AARCH64) SPI_TARGET=nxp endif + ifeq ($(TARGET),cm4) + # Raspberry Pi Compute Module 4 - Broadcom BCM2711, Cortex-A72 + ARCH_FLAGS=-mcpu=cortex-a72+crypto -march=armv8-a+crypto -mtune=cortex-a72 + # -mstrict-align: wolfBoot runs with the MMU off (simple startup), so data + # accesses are Device memory where unaligned access faults. Required for the + # FIPS in-core HMAC over the code region (NO_ARM_ASM drops the asm path that + # otherwise sets this). + CFLAGS+=$(ARCH_FLAGS) -DCORTEX_A72 -mstrict-align + endif + # Default ARM ASM setting for unrecognized AARCH64 targets - ifeq ($(filter zynq versal nxp_ls1028a,$(TARGET)),) + ifeq ($(filter zynq versal nxp_ls1028a cm4,$(TARGET)),) NO_ARM_ASM?=1 endif diff --git a/config/examples/cm4.config b/config/examples/cm4.config new file mode 100644 index 0000000000..ea9ff84e5b --- /dev/null +++ b/config/examples/cm4.config @@ -0,0 +1,18 @@ +ARCH?=AARCH64 +TARGET?=cm4 +SIGN?=ECC384 +HASH?=SHA384 +DEBUG?=1 +VTOR?=1 +SPMATH?=1 +IMAGE_HEADER_SIZE?=1024 +PKA?=0 +WOLFTPM?=0 +DEBUG_UART?=0 +NO_XIP?=1 +NO_QNX?=1 +WOLFBOOT_SECTOR_SIZE=0x400 +WOLFBOOT_NO_PARTITIONS=1 +WOLFBOOT_RAMBOOT_MAX_SIZE=0x20000000 +WOLFBOOT_LOAD_ADDRESS?=0x3080000 +WOLFBOOT_LOAD_DTS_ADDRESS?=0x400000 diff --git a/config/examples/cm4_sdcard.config b/config/examples/cm4_sdcard.config new file mode 100644 index 0000000000..3f230c30ee --- /dev/null +++ b/config/examples/cm4_sdcard.config @@ -0,0 +1,39 @@ +# Raspberry Pi CM4 (BCM2711) - eMMC/SD A/B disk boot (Phase 2) +# +# Boots from the BCM2711 EMMC2 controller (Arasan SDHCI @ 0xFE340000), which +# drives the onboard eMMC (eMMC variants) or the microSD (CM4 Lite). wolfBoot +# reads GPT A/B image partitions via update_disk.c and boots the highest valid +# version with rollback. +# +# NOTE: the EMMC2 platform glue in hal/cm4.c is bring-up scaffolding pending +# on-hardware validation (controller clock/pinmux state left by the GPU +# firmware, card-detect wiring on the carrier). Use SDHCI_FORCE_CARD_DETECT +# for the embedded eMMC path. +ARCH?=AARCH64 +TARGET?=cm4 +SIGN?=ECC384 +HASH?=SHA384 +IMAGE_HEADER_SIZE?=1024 +DEBUG?=0 +DEBUG_UART?=1 +DISK_SDCARD?=1 +DISK_EMMC?=0 +CFLAGS_EXTRA+=-DSDHCI_FORCE_CARD_DETECT +EXT_FLASH?=0 +NO_XIP=1 +NO_QNX?=1 +ELF?=1 +VTOR?=1 +SPMATH?=1 +PKA?=0 +WOLFTPM?=0 +WOLFBOOT_NO_PARTITIONS=1 +CFLAGS_EXTRA+=-DBOOT_PART_A=1 +CFLAGS_EXTRA+=-DBOOT_PART_B=2 +CFLAGS_EXTRA+=-DDISK_BLOCK_SIZE=0x80000 +WOLFBOOT_LOAD_ADDRESS?=0x10000000 +WOLFBOOT_RAMBOOT_MAX_SIZE=0x2BC00000 +WOLFBOOT_LOAD_DTS_ADDRESS?=0x1000 +WOLFBOOT_PARTITION_BOOT_ADDRESS=0x80200000 +WOLFBOOT_PARTITION_SIZE=0x4000000 +WOLFBOOT_SECTOR_SIZE=0x1000 diff --git a/docs/Targets.md b/docs/Targets.md index 35324a7163..635cd5dad0 100644 --- a/docs/Targets.md +++ b/docs/Targets.md @@ -6,6 +6,7 @@ This README describes configuration of supported targets. * [Simulated](#simulated) * [Cortex-A53 / Raspberry PI 3](#cortex-a53--raspberry-pi-3-experimental) +* [Cortex-A72 / Raspberry Pi Compute Module 4](#cortex-a72--raspberry-pi-compute-module-4-bcm2711) * [Cypress PSoC-6](#cypress-psoc-6) * [Infineon AURIX TC3xx](#infineon-aurix-tc3xx) * [Intel x86-64 Intel FSP](#intel-x86_64-with-intel-fsp-support) @@ -3695,6 +3696,79 @@ qemu-system-aarch64 -M raspi3b -m 1024 -serial stdio -kernel wolfboot_linux_rasp ``` +## Cortex-A72 / Raspberry Pi Compute Module 4 (BCM2711) + +wolfBoot runs on the Raspberry Pi Compute Module 4 (CM4), a Broadcom BCM2711 with a quad-core Cortex-A72 (AArch64). wolfBoot takes the place of the second-stage OS loader: the BCM2711 boot ROM loads the VideoCore firmware, the firmware loads `kernel8.img` from the boot partition, and that `kernel8.img` is wolfBoot. wolfBoot then verifies the signed application image and boots it, extending the platform root of trust into the OS. + +``` +BCM2711 boot ROM -> SPI EEPROM bootloader -> VideoCore firmware (start4.elf) + -> kernel8.img (wolfBoot) -> verify (ECDSA/SHA) -> application +``` + +On CM4 modules with onboard eMMC the boot files live on the eMMC FAT boot partition; on CM4 Lite they live on a microSD. Either way the medium hangs off the BCM2711 EMMC2 controller (a standard SDHCI v3.0 Arasan block at `0xFE340000`). + +### Building + +``` +cp config/examples/cm4.config .config +make CROSS_COMPILE=aarch64-none-elf- +``` + +The example uses `SIGN=ECC384 HASH=SHA384` (both FIPS-approved). wolfBoot is entered by the firmware at `0x80000` at EL2, matching `hal/cm4.ld`. The image is loaded from RAM: wolfBoot reads the signed application at `kernel_addr` (`0x140000`), verifies it, copies it to `WOLFBOOT_LOAD_ADDRESS`, and boots. + +### Signing and assembling the boot image + +Sign the application, then concatenate wolfBoot and the signed image so the signed image lands at `kernel_addr` (`0x140000` = `0x80000` load + `0xC0000`): + +``` +make keytools tools/bin-assemble/bin-assemble +IMAGE_HEADER_SIZE=1024 ./tools/keytools/sign --ecc384 --sha384 \ + app.bin wolfboot_signing_private_key.der 1 +tools/bin-assemble/bin-assemble kernel8.img \ + 0x0 wolfboot.bin \ + 0xC0000 app_v1_signed.bin +``` + +### config.txt + +The CM4 UART on GPIO14/15 defaults to the mini-UART because the PL011 is used by Bluetooth. wolfBoot drives the PL011, so route it to the header and fix a known UART clock: + +``` +arm_64bit=1 +kernel=kernel8.img +enable_uart=1 +uart_2ndstage=1 +dtoverlay=disable-bt +init_uart_clock=48000000 +init_uart_baud=115200 +``` + +### Flashing + +- CM4 Lite: write `kernel8.img` + the RPi firmware (`start4.elf`, `fixup4.dat`) + `config.txt` to the microSD FAT boot partition. +- CM4 with eMMC: put the module in USB boot mode (nRPIBOOT), run `rpiboot` to expose the eMMC as USB mass storage, and write the same files to its FAT boot partition. See https://github.com/raspberrypi/usbboot . + +### Boot output + +With `DEBUG_UART=1`, a successful authenticated boot prints (115200 8N1): + +``` +wolfBoot CM4 (BCM2711 Cortex-A72) hal_init, EL2 +Trying partition 0 at 0x140000 +Checking integrity...done +Verifying signature...done +Firmware Valid +Booting at 0x3080000 +``` + +### Optional: eMMC/SD A/B updates + +`config/examples/cm4_sdcard.config` enables the disk updater (`DISK_SDCARD`/`DISK_EMMC`), driving the BCM2711 EMMC2 controller through the generic SDHCI driver (`src/sdhci.c`) for A/B image partitions on the boot medium. This path is provided as bring-up scaffolding and is not yet hardware-validated. + +### FIPS 140-3 + +The CM4 target uses `SIGN=ECC384 HASH=SHA384` (FIPS-approved) and can perform its signature verification with the wolfCrypt FIPS 140-3 validated module. The on-target harness in `test-app/app_cm4.c` registers a FIPS callback and prints the runtime in-core integrity hash over the UART for the `verifyCore[]` bootstrap. See [FIPS.md](FIPS.md) for the full build and hash-sealing procedure. + ## Xilinx Zynq UltraScale AMD Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit - Quad-core ARM Cortex-A53 (plus dual Cortex-R5). diff --git a/hal/cm4.c b/hal/cm4.c new file mode 100644 index 0000000000..2a041ff051 --- /dev/null +++ b/hal/cm4.c @@ -0,0 +1,314 @@ +/* cm4.c + * + * HAL for the Raspberry Pi Compute Module 4 (CM4): Broadcom BCM2711, + * quad-core Cortex-A72 (ARMv8-A). + * + * The VideoCore GPU firmware loads wolfBoot (as kernel8.img) to 0x80000 and + * releases the A72 cores; wolfBoot verifies the appended signed payload and + * boots it from RAM. hal_flash_* are no-ops (no in-place flash in this mode). + * Optional eMMC/SD A/B via the generic SDHCI driver is at the end of the file. + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ +#include +#include +#include +#include +#include "image.h" +#include "printf.h" +#include "hal/cm4.h" +#ifndef ARCH_AARCH64 +# error "wolfBoot cm4 HAL: wrong architecture selected. Please compile with ARCH=AARCH64." +#endif + +/* Hardware register map (bases, UART, EMMC2/SDHCI) is in hal/cm4.h */ + +/* Fixed addresses (provided by the linker script) */ +extern void *kernel_addr, *update_addr, *dts_addr; + +#if defined(DEBUG_UART) +static void uart_tx(char c) +{ + while (*UART0_FR & 0x20) /* TXFF: wait while FIFO full */ + ; + *UART0_DR = c; +} + +void uart_write(const char* buf, uint32_t sz) +{ + while (sz-- > 0 && *buf) + uart_tx(*buf++); +} + +void uart_init(void) +{ + /* The VideoCore firmware has already routed the PL011 to GPIO14/15 + * (dtoverlay=disable-bt) and set init_uart_clock=48MHz. Program the PL011 + * for 115200 8N1 directly, without the VideoCore mailbox (a mailbox poll + * that never returns post-handoff would hang before any output). + * 48MHz UARTCLK: BAUDDIV = 48e6/(16*115200) = 26.04 -> IBRD 26, FBRD 3. */ + *UART0_CR = 0; + *UART0_ICR = 0x7FF; + *UART0_IBRD = 26; + *UART0_FBRD = 3; + *UART0_LCRH = (1 << 4) | (1 << 5) | (1 << 6); /* FIFO, 8-bit */ + *UART0_CR = (1 << 0) | (1 << 8) | (1 << 9); /* enable UART, TX, RX */ +} +#endif /* DEBUG_UART */ + +void* hal_get_primary_address(void) +{ + return (void*)&kernel_addr; +} + +void* hal_get_update_address(void) +{ + return (void*)&update_addr; +} + +void* hal_get_dts_address(void) +{ + return (void*)&dts_addr; +} + +void* hal_get_dts_update_address(void) +{ + return NULL; /* Not yet supported */ +} + +#ifdef EXT_FLASH +int ext_flash_read(unsigned long address, uint8_t *data, int len) +{ + XMEMCPY(data, (void *)address, len); + return len; +} + +int ext_flash_erase(unsigned long address, int len) +{ + XMEMSET((void *)address, 0xFF, len); + return len; +} + +int ext_flash_write(unsigned long address, const uint8_t *data, int len) +{ + XMEMCPY((void *)address, data, len); + return len; +} + +void ext_flash_lock(void) +{ +} + +void ext_flash_unlock(void) +{ +} +#endif /* EXT_FLASH */ + +void hal_init(void) +{ +#if defined(DEBUG_UART) + unsigned long el; + uart_init(); + __asm__ volatile("mrs %0, CurrentEL" : "=r"(el)); + wolfBoot_printf("wolfBoot CM4 (BCM2711 Cortex-A72) hal_init, EL%d\n", + (int)((el >> 2) & 0x3)); +#endif +} + +void hal_prepare_boot(void) +{ +} + +#if defined(HAVE_FIPS) +/* FIPS DRBG entropy seed from the BCM2711 RNG200 hardware TRNG. Registered via + * CUSTOM_RAND_GENERATE_SEED in include/user_settings.h. The RNG200 has NIST + * SP800-90B startup/continuous health tests in hardware. */ +int wolfBoot_fips_seed(unsigned char* output, unsigned int sz) +{ + static int rng_inited = 0; + unsigned int pos = 0; + unsigned int guard; + + if (!rng_inited) { + /* iproc-rng200 bring-up: disable RBG, soft-reset the RBG then RNG + * cores, clear pending interrupt status, then re-enable the RBG. */ + *RNG_CTRL = 0; + *RNG_RBG_SOFT_RESET = 1; + *RNG_RBG_SOFT_RESET = 0; + *RNG_SOFT_RESET = 1; + *RNG_SOFT_RESET = 0; + *RNG_INT_STATUS = 0xFFFFFFFF; /* write-1-to-clear all pending status */ + *RNG_CTRL = RNG200_CTRL_RBGEN; + rng_inited = 1; + } + + while (pos < sz) { + unsigned int word, n, i; + /* wait for at least one 32-bit word in the FIFO (bounded) */ + guard = 0; + while ((*RNG_FIFO_COUNT & 0xFF) == 0) { + if (++guard > 200000000U) { +#if defined(DEBUG_UART) + wolfBoot_printf("RNG200 FIFO timeout int=0x%08x ctrl=0x%08x\n", + (unsigned)*RNG_INT_STATUS, (unsigned)*RNG_CTRL); +#endif + return -1; + } + } + word = *RNG_FIFO_DATA; + n = (sz - pos) < 4 ? (sz - pos) : 4; + for (i = 0; i < n; i++) + output[pos++] = (unsigned char)(word >> (i * 8)); + } + +#if defined(DEBUG_UART) + { + static int traced = 0; + if (!traced) { + wolfBoot_printf("RNG200 seed %02x %02x %02x %02x %02x %02x %02x %02x\n", + output[0], output[1], output[2], output[3], + output[4], output[5], output[6], output[7]); + traced = 1; + } + } +#endif + return 0; +} +#endif /* HAVE_FIPS */ + +int RAMFUNCTION hal_flash_write(uintptr_t address, const uint8_t *data, int len) +{ + (void)address; (void)data; (void)len; + return 0; +} + +void RAMFUNCTION hal_flash_unlock(void) +{ +} + +void RAMFUNCTION hal_flash_lock(void) +{ +} + +int RAMFUNCTION hal_flash_erase(uintptr_t address, int len) +{ + (void)address; (void)len; + return 0; +} + +#if defined(DISK_SDCARD) || defined(DISK_EMMC) +/* BCM2711 EMMC2 platform glue for the generic SDHCI driver (src/sdhci.c). + * EMMC2 is a standard SDHCI v3.0 Arasan block at 0xFE340000. The driver uses + * Cadence-style SRS offsets (0x200 + std); translate them to the standard + * Arasan layout, mirroring the ZynqMP path in hal/zynq.c. NOTE: not yet + * hardware-validated; clock/caps/card-detect quirks may be required once + * validated on hardware. */ +#include "sdhci.h" + +uint32_t sdhci_reg_read(uint32_t offset) +{ + volatile uint8_t *base = (volatile uint8_t *)BCM2711_EMMC2_BASE; + + if (offset >= CADENCE_SRS_OFFSET) { + uint32_t std_off = offset - CADENCE_SRS_OFFSET; + uint32_t val; + + if (std_off == 0x58) /* SRS22 -> legacy SDMA address (SRS00) */ + return *((volatile uint32_t *)(base + STD_SDHCI_SDMA_ADDR)); + if (std_off == 0x5C) /* SRS23: no 64-bit addressing on v3.0 */ + return 0; + val = *((volatile uint32_t *)(base + std_off)); + if (std_off == 0x40) /* SRS16 Capabilities: mask A64S (no HV4E) */ + val &= ~SDHCI_SRS16_A64S; + return val; + } + return 0; /* HRS region not present on this Arasan block */ +} + +void sdhci_reg_write(uint32_t offset, uint32_t val) +{ + volatile uint8_t *base = (volatile uint8_t *)BCM2711_EMMC2_BASE; + uint32_t std_off; + + if (offset < CADENCE_SRS_OFFSET) + return; /* HRS region not present */ + std_off = offset - CADENCE_SRS_OFFSET; + + /* SRS10 (0x28): Host Control 1 / Power / Block Gap / Wakeup (8-bit each) */ + if (std_off == 0x28) { + *((volatile uint8_t *)(base + STD_SDHCI_HOST_CTRL1)) = (uint8_t)val; + *((volatile uint8_t *)(base + STD_SDHCI_POWER_CTRL)) = (uint8_t)(val >> 8); + *((volatile uint8_t *)(base + STD_SDHCI_BLKGAP_CTRL)) = (uint8_t)(val >> 16); + *((volatile uint8_t *)(base + STD_SDHCI_WAKEUP_CTRL)) = (uint8_t)(val >> 24); + return; + } + /* SRS11 (0x2C): Clock Control (16-bit) / Timeout / Software Reset */ + if (std_off == 0x2C) { + *((volatile uint16_t *)(base + STD_SDHCI_CLK_CTRL)) = (uint16_t)val; + *((volatile uint8_t *)(base + STD_SDHCI_TIMEOUT_CTRL)) = (uint8_t)(val >> 16); + *((volatile uint8_t *)(base + STD_SDHCI_SW_RESET)) = (uint8_t)(val >> 24); + return; + } + if (std_off == 0x58) { /* SRS22 -> legacy SDMA address; write restarts DMA */ + *((volatile uint32_t *)(base + STD_SDHCI_SDMA_ADDR)) = val; + return; + } + if (std_off == 0x5C) /* SRS23: no 64-bit addressing on v3.0 */ + return; + if (std_off == STD_SDHCI_HOST_CTRL2) /* SRS15: mask unsupported HV4E/A64 */ + val &= ~(SDHCI_SRS15_HV4E | SDHCI_SRS15_A64); + *((volatile uint32_t *)(base + std_off)) = val; +} + +void sdhci_platform_init(void) +{ + /* The GPU firmware already brought up the EMMC2 clock/pinmux; just issue a + * controller soft reset and wait for it to clear. */ + volatile uint8_t *base = (volatile uint8_t *)BCM2711_EMMC2_BASE; + volatile int i; + + *((volatile uint8_t *)(base + STD_SDHCI_SW_RESET)) = STD_SDHCI_SRA; + for (i = 0; i < 100000; i++) { + if ((*((volatile uint8_t *)(base + STD_SDHCI_SW_RESET)) & STD_SDHCI_SRA) == 0) + break; + } +} + +void sdhci_platform_irq_init(void) +{ + /* Polled mode; no IRQ wiring needed for the boot path. */ +} + +void sdhci_platform_set_bus_mode(int is_emmc) +{ + (void)is_emmc; /* handled by the generic driver via Host Control 1 */ +} + +/* Microseconds from the ARMv8 generic timer (SDHCI udelay + disk updater). + * Falls back to the BCM2711 system counter frequency if CNTFRQ_EL0 is 0. */ +uint64_t hal_get_timer_us(void) +{ + uint64_t count, freq; + __asm__ volatile("mrs %0, CNTPCT_EL0" : "=r"(count)); + __asm__ volatile("mrs %0, CNTFRQ_EL0" : "=r"(freq)); + if (freq == 0) + freq = BCM2711_TIMER_CLK_FREQ; + return (uint64_t)(((__uint128_t)count * 1000000ULL) / freq); +} +#endif /* DISK_SDCARD || DISK_EMMC */ diff --git a/hal/cm4.h b/hal/cm4.h new file mode 100644 index 0000000000..7b5d650364 --- /dev/null +++ b/hal/cm4.h @@ -0,0 +1,88 @@ +/* cm4.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +/* Raspberry Pi Compute Module 4 (CM4) - Broadcom BCM2711, Cortex-A72. + * Hardware register map (bases, UART, EMMC2/SDHCI) shared by the HAL and the + * test application. This header is also included from boot_aarch64_start.S, so + * pointer-cast accessors are guarded with __ASSEMBLER__. */ + +#ifndef _CM4_H_ +#define _CM4_H_ + +/* Select the compact AArch64 startup path in boot_aarch64_start.S */ +#define USE_BUILTIN_STARTUP +#define USE_SIMPLE_STARTUP + +/* BCM2711 peripheral base addresses (low-peripheral 0xFE000000 view). + * Integer literals - safe to include from assembly. */ +#define BCM2711_MMIO_BASE 0xFE000000 +#define BCM2711_GPIO_BASE (BCM2711_MMIO_BASE + 0x200000) +#define BCM2711_UART0_BASE (BCM2711_GPIO_BASE + 0x1000) /* PL011 */ +#define BCM2711_EMMC2_BASE (BCM2711_MMIO_BASE + 0x340000) /* Arasan SDHCI */ +#define BCM2711_RNG_BASE (BCM2711_MMIO_BASE + 0x104000) /* RNG200 TRNG */ + +/* RNG200 (iproc-rng200) register offsets */ +#define RNG200_CTRL 0x00 /* bit0 RBGEN = enable */ +#define RNG200_SOFT_RESET 0x04 +#define RNG200_RBG_SOFT_RESET 0x08 +#define RNG200_INT_STATUS 0x18 +#define RNG200_FIFO_DATA 0x20 +#define RNG200_FIFO_COUNT 0x24 /* [7:0] = words available */ +#define RNG200_CTRL_RBGEN 0x00000001 + +/* BCM2711 system counter frequency (fallback if CNTFRQ_EL0 reads 0) */ +#define BCM2711_TIMER_CLK_FREQ 54000000ULL + +/* SDHCI register offsets used by the EMMC2 glue. The generic SDHCI driver + * addresses registers with Cadence-style SRS offsets (0x200 + std); the glue + * translates to the standard Arasan layout below. Integers, assembler-safe. */ +#define CADENCE_SRS_OFFSET 0x200 +#define STD_SDHCI_SDMA_ADDR 0x00 /* SDMA System Address (32-bit) */ +#define STD_SDHCI_HOST_CTRL1 0x28 +#define STD_SDHCI_POWER_CTRL 0x29 +#define STD_SDHCI_BLKGAP_CTRL 0x2A +#define STD_SDHCI_WAKEUP_CTRL 0x2B +#define STD_SDHCI_CLK_CTRL 0x2C +#define STD_SDHCI_TIMEOUT_CTRL 0x2E +#define STD_SDHCI_SW_RESET 0x2F +#define STD_SDHCI_HOST_CTRL2 0x3C +#define STD_SDHCI_SRA 0x01 /* Software Reset for All */ + +#ifndef __ASSEMBLER__ +/* PL011 UART0 register accessors */ +#define UART0_DR ((volatile unsigned int*)(BCM2711_UART0_BASE+0x00)) +#define UART0_FR ((volatile unsigned int*)(BCM2711_UART0_BASE+0x18)) +#define UART0_IBRD ((volatile unsigned int*)(BCM2711_UART0_BASE+0x24)) +#define UART0_FBRD ((volatile unsigned int*)(BCM2711_UART0_BASE+0x28)) +#define UART0_LCRH ((volatile unsigned int*)(BCM2711_UART0_BASE+0x2C)) +#define UART0_CR ((volatile unsigned int*)(BCM2711_UART0_BASE+0x30)) +#define UART0_ICR ((volatile unsigned int*)(BCM2711_UART0_BASE+0x44)) + +/* RNG200 hardware TRNG register accessors */ +#define RNG_CTRL ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_CTRL)) +#define RNG_SOFT_RESET ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_SOFT_RESET)) +#define RNG_RBG_SOFT_RESET ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_RBG_SOFT_RESET)) +#define RNG_INT_STATUS ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_INT_STATUS)) +#define RNG_FIFO_DATA ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_FIFO_DATA)) +#define RNG_FIFO_COUNT ((volatile unsigned int*)(BCM2711_RNG_BASE+RNG200_FIFO_COUNT)) +#endif /* !__ASSEMBLER__ */ + +#endif /* _CM4_H_ */ diff --git a/hal/cm4.ld b/hal/cm4.ld new file mode 100644 index 0000000000..aff7e3dc6e --- /dev/null +++ b/hal/cm4.ld @@ -0,0 +1,71 @@ +/* cm4.ld + * + * Linker script for the Raspberry Pi Compute Module 4 (BCM2711, Cortex-A72). + * + * The VideoCore GPU firmware loads kernel8.img to 0x80000 and releases the + * A72 cores there. DDR_MEM length covers the 1GB low-peripheral view common + * to all CM4 RAM variants (1/2/4/8 GB); the peripheral block sits above at + * 0xFE000000 and is not mapped here. + */ +MEMORY +{ + DDR_MEM(rwx): ORIGIN = 0x00080000, LENGTH = 0x3c000000 +} +ENTRY(_vector_table); + +SECTIONS +{ + .text : + { + _start_text = .; + KEEP(*(.boot*)) + *(.text*) + *(.rodata*) + *(.note.*) + . = ALIGN(4); + _end_text = .; + } > DDR_MEM + .edidx : + { + . = ALIGN(4); + *(.ARM.exidx*) + } > DDR_MEM + + .data : + { + _start_data = .; + KEEP(*(.data*)) + . = ALIGN(4); + KEEP(*(.ramcode)) + . = ALIGN(4); + _end_data = .; + } > DDR_MEM + + .bss (NOLOAD) : + { + _start_bss = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + _end_bss = .; + __bss_end__ = .; + _end = .; + } > DDR_MEM + . = ALIGN(8); + /* Heap start for the newlib sbrk (FIPS module malloc). Grows up into free + * DDR; the stack lives at END_STACK (0x80000) and grows down. */ + PROVIDE(end = .); + PROVIDE(__end__ = .); + PROVIDE(_heap_start = .); +} + +END_STACK = _start_text; +kernel_addr = 0x0140000; +update_addr = 0x1140000; +dts_addr = 0x00a0000; +kernel_load_addr = 0x20000000; +dts_load_addr = 0x21000000; + +_wolfboot_partition_boot_address = kernel_addr; +_wolfboot_partition_update_address = update_addr; diff --git a/src/boot_aarch64_start.S b/src/boot_aarch64_start.S index 58066d1424..d3de26a131 100644 --- a/src/boot_aarch64_start.S +++ b/src/boot_aarch64_start.S @@ -38,6 +38,10 @@ #include "hal/raspi3.h" #endif +#ifdef TARGET_cm4 +#include "hal/cm4.h" +#endif + /* GICv2 Register Offsets */ #ifndef GICD_BASE #define GICD_BASE 0xF9010000 diff --git a/test-app/app_cm4.c b/test-app/app_cm4.c new file mode 100644 index 0000000000..865479cd8f --- /dev/null +++ b/test-app/app_cm4.c @@ -0,0 +1,128 @@ +/* app_cm4.c + * + * Test application for Raspberry Pi CM4 (BCM2711). Prints a banner over the + * PL011 UART and, when built against wolfCrypt FIPS (HAVE_FIPS), runs the + * power-on self-tests and registers a FIPS callback that reports the runtime + * in-core integrity hash for the verifyCore[] bootstrap. + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include +#include "wolfboot/wolfboot.h" +#include "hal/cm4.h" /* BCM2711 UART register map */ + +#ifdef HAVE_FIPS +#include +#include +#include +#endif + +#ifdef TARGET_cm4 + +static void uart_init(void) +{ + /* PL011 for 115200 8N1 from the 48 MHz UART clock (see hal/cm4.c) */ + *UART0_CR = 0; + *UART0_ICR = 0x7FF; + *UART0_IBRD = 26; + *UART0_FBRD = 3; + *UART0_LCRH = (1 << 4) | (1 << 5) | (1 << 6); + *UART0_CR = (1 << 0) | (1 << 8) | (1 << 9); +} + +static void uart_putc(char c) +{ + while (*UART0_FR & 0x20) /* wait while TX FIFO full */ + ; + *UART0_DR = (unsigned int)c; +} + +static void uart_puts(const char* s) +{ + while (*s) { + if (*s == '\n') + uart_putc('\r'); + uart_putc(*s++); + } +} + +static void uart_putdec(int v) +{ + char buf[12]; + unsigned int u; + int i = 0; + + if (v < 0) { + uart_putc('-'); + u = (unsigned int)(-v); + } + else { + u = (unsigned int)v; + } + do { + buf[i++] = (char)('0' + (u % 10)); + u /= 10; + } while (u != 0); + while (i > 0) + uart_putc(buf[--i]); +} + +#ifdef HAVE_FIPS +/* wolfCrypt FIPS callback. On an in-core integrity mismatch (IN_CORE_FIPS_E) + * the module reports the runtime hash here; copy it into verifyCore[] in + * wolfcrypt/src/fips_test.c and rebuild to seal the module boundary. */ +static void cm4_fipsCb(int ok, int err, const char* hash) +{ + uart_puts("FIPS callback: ok="); + uart_putdec(ok); + uart_puts(" err="); + uart_putdec(err); + uart_puts("\nhash = "); + uart_puts(hash != NULL ? hash : "(null)"); + uart_puts("\n"); + if (err == IN_CORE_FIPS_E) { + uart_puts("In-core integrity mismatch: copy the hash above into\n"); + uart_puts("verifyCore[] in wolfcrypt/src/fips_test.c and rebuild.\n"); + } +} +#endif /* HAVE_FIPS */ + +void main(void) +{ + uart_init(); + uart_puts("\n=== wolfBoot CM4 test-app ===\n"); + +#ifdef HAVE_FIPS + uart_puts("wolfCrypt FIPS 140-3 power-on self-test\n"); + wolfCrypt_SetCb_fips(cm4_fipsCb); + if (wc_RunAllCast_fips() == 0) + uart_puts("FIPS CASTs: PASS\n"); + else + uart_puts("FIPS CASTs: FAIL (see callback output above)\n"); + uart_puts("FIPS status: "); + uart_putdec(wolfCrypt_GetStatus_fips()); + uart_puts("\n"); +#endif /* HAVE_FIPS */ + + uart_puts("test-app done; halting.\n"); + while (1) + ; +} +#endif /* TARGET_cm4 */ From 21cf9efb76ecdbd5ea930cee985ed7b1e8184c0e Mon Sep 17 00:00:00 2001 From: David Garske Date: Fri, 10 Jul 2026 17:30:27 -0700 Subject: [PATCH 2/2] cm4: add wolfCrypt FIPS 140-3 support + CI, SDHCI unit test, review fixes --- .github/workflows/test-build-aarch64.yml | 16 ++ .github/workflows/test-configs.yml | 22 +++ config/examples/cm4.config | 10 ++ config/examples/cm4_sdcard.config | 11 +- config/examples/sim-fips.config | 22 +++ docs/FIPS.md | 82 ++++++++++ docs/README.md | 1 + docs/Targets.md | 2 +- hal/cm4.c | 186 +++++++++++++++++++++-- hal/cm4.h | 3 + hal/sim.c | 28 ++++ include/user_settings.h | 78 +++++++++- options.mk | 45 ++++++ src/boot_aarch64_start.S | 44 ++++++ src/loader.c | 31 ++++ test-app/app_cm4.c | 8 +- tools/unit-tests/Makefile | 6 +- tools/unit-tests/unit-cm4-sdhci.c | 162 ++++++++++++++++++++ 18 files changed, 733 insertions(+), 24 deletions(-) create mode 100644 config/examples/sim-fips.config create mode 100644 docs/FIPS.md create mode 100644 tools/unit-tests/unit-cm4-sdhci.c diff --git a/.github/workflows/test-build-aarch64.yml b/.github/workflows/test-build-aarch64.yml index 2ace6bcada..6f6e1d1d9b 100644 --- a/.github/workflows/test-build-aarch64.yml +++ b/.github/workflows/test-build-aarch64.yml @@ -18,6 +18,12 @@ on: required: false type: boolean default: false + fips: + # Download the FIPS-ready wolfSSL tree into ../ before building, for a + # build-only FIPS=1 verification (see WOLFBOOT_LIB_WOLFSSL in make-args). + required: false + type: boolean + default: false jobs: @@ -123,6 +129,16 @@ jobs: unsigned long psu_ddr_qos_init_data(void) { return 1UL; } STUB + - name: Download FIPS-ready wolfSSL + if: ${{ inputs.fips }} + run: | + set -euxo pipefail + sudo apt-get install -y unzip + curl -fsSL -o /tmp/wolfssl-fips-ready.zip \ + https://www.wolfssl.com/wolfssl-5.9.2-gplv3-fips-ready.zip + unzip -q /tmp/wolfssl-fips-ready.zip -d .. + test -f ../wolfssl-5.9.2-gplv3-fips-ready/wolfcrypt/src/fips.c + - name: Build wolfboot run: | make ${{inputs.make-args}} diff --git a/.github/workflows/test-configs.yml b/.github/workflows/test-configs.yml index 411299218a..7357fdc1e2 100644 --- a/.github/workflows/test-configs.yml +++ b/.github/workflows/test-configs.yml @@ -359,6 +359,28 @@ jobs: config-file: ./config/examples/raspi3-encrypted.config make-args: wolfboot.bin CROSS_COMPILE=aarch64-linux-gnu- + cm4_test: + uses: ./.github/workflows/test-build-aarch64.yml + with: + arch: aarch64 + config-file: ./config/examples/cm4.config + make-args: wolfboot.bin + + cm4_sdcard_test: + uses: ./.github/workflows/test-build-aarch64.yml + with: + arch: aarch64 + config-file: ./config/examples/cm4_sdcard.config + make-args: wolfboot.bin + + cm4_fips_test: + uses: ./.github/workflows/test-build-aarch64.yml + with: + arch: aarch64 + config-file: ./config/examples/cm4.config + make-args: wolfboot.bin FIPS=1 WOLFBOOT_LIB_WOLFSSL=../wolfssl-5.9.2-gplv3-fips-ready NO_ARM_ASM=1 + fips: true + sim_tfm_smallstack_test: uses: ./.github/workflows/test-build.yml with: diff --git a/config/examples/cm4.config b/config/examples/cm4.config index ea9ff84e5b..317093c7d3 100644 --- a/config/examples/cm4.config +++ b/config/examples/cm4.config @@ -1,3 +1,13 @@ +# Raspberry Pi CM4 (BCM2711) - RAM-boot authenticated boot. +# +# For wolfCrypt FIPS 140-3, build with FIPS=1 pointing at a FIPS / FIPS-ready +# wolfSSL tree. The FIPS module uses portable-C crypto, so NO_ARM_ASM is +# required. Entropy comes from the BCM2711 RNG200 hardware TRNG (hal/cm4.c). +# See docs/FIPS.md for the in-core hash-seal procedure (done on-target). e.g.: +# make FIPS=1 WOLFBOOT_LIB_WOLFSSL=../wolfssl-5.9.2-gplv3-fips-ready NO_ARM_ASM=1 +#FIPS?=1 +#WOLFBOOT_LIB_WOLFSSL?=../wolfssl-5.9.2-gplv3-fips-ready +#NO_ARM_ASM?=1 ARCH?=AARCH64 TARGET?=cm4 SIGN?=ECC384 diff --git a/config/examples/cm4_sdcard.config b/config/examples/cm4_sdcard.config index 3f230c30ee..06963d7db2 100644 --- a/config/examples/cm4_sdcard.config +++ b/config/examples/cm4_sdcard.config @@ -1,4 +1,4 @@ -# Raspberry Pi CM4 (BCM2711) - eMMC/SD A/B disk boot (Phase 2) +# Raspberry Pi CM4 (BCM2711) - eMMC/SD A/B disk boot. # # Boots from the BCM2711 EMMC2 controller (Arasan SDHCI @ 0xFE340000), which # drives the onboard eMMC (eMMC variants) or the microSD (CM4 Lite). wolfBoot @@ -9,6 +9,15 @@ # on-hardware validation (controller clock/pinmux state left by the GPU # firmware, card-detect wiring on the carrier). Use SDHCI_FORCE_CARD_DETECT # for the embedded eMMC path. +# +# For wolfCrypt FIPS 140-3, build with FIPS=1 pointing at a FIPS / FIPS-ready +# wolfSSL tree. The FIPS module uses portable-C crypto, so NO_ARM_ASM is +# required. Entropy comes from the BCM2711 RNG200 hardware TRNG (hal/cm4.c). +# See docs/FIPS.md for the in-core hash-seal procedure (done on-target). e.g.: +# make FIPS=1 WOLFBOOT_LIB_WOLFSSL=../wolfssl-5.9.2-gplv3-fips-ready NO_ARM_ASM=1 +#FIPS?=1 +#WOLFBOOT_LIB_WOLFSSL?=../wolfssl-5.9.2-gplv3-fips-ready +#NO_ARM_ASM?=1 ARCH?=AARCH64 TARGET?=cm4 SIGN?=ECC384 diff --git a/config/examples/sim-fips.config b/config/examples/sim-fips.config new file mode 100644 index 0000000000..360331ad51 --- /dev/null +++ b/config/examples/sim-fips.config @@ -0,0 +1,22 @@ +# wolfBoot simulator build using the wolfCrypt FIPS 140-3 module. +# Point WOLFBOOT_LIB_WOLFSSL at an unpacked FIPS (or FIPS-ready) wolfSSL tree. +# Prototype target for the CM4 FIPS integration (see docs/FIPS.md). +ARCH=sim +TARGET=sim +SIGN?=ECC384 +HASH?=SHA384 +FIPS?=1 +WOLFBOOT_LIB_WOLFSSL?=../wolfssl-5.9.2-gplv3-fips-ready +WOLFBOOT_SMALL_STACK?=0 +SPI_FLASH=0 +DEBUG=1 + +# sizes should be multiple of system page size +WOLFBOOT_PARTITION_SIZE=0x40000 +WOLFBOOT_SECTOR_SIZE=0x1000 +WOLFBOOT_PARTITION_BOOT_ADDRESS=0x80000 +WOLFBOOT_PARTITION_UPDATE_ADDRESS=0x100000 +WOLFBOOT_PARTITION_SWAP_ADDRESS=0x180000 + +# required for keytools +WOLFBOOT_FIXED_PARTITIONS=1 diff --git a/docs/FIPS.md b/docs/FIPS.md new file mode 100644 index 0000000000..0efd109314 --- /dev/null +++ b/docs/FIPS.md @@ -0,0 +1,82 @@ +# wolfBoot with wolfCrypt FIPS 140-3 + +This page explains how wolfBoot performs its firmware signature verification with the wolfCrypt FIPS 140-3 module, and what a fully CMVP-validated deployment additionally requires. Read it before making any FIPS claim about a wolfBoot deployment. + +## Two distinct things: approved algorithms vs. a validated module + +FIPS 140-3 has two separate requirements that are easy to conflate: + +1. Using FIPS **approved algorithms** for the security-relevant operations (here: image signature verification and hashing). +2. Performing those operations inside the **CMVP-validated wolfCrypt module** boundary, with the power-on self-test (POST), the in-core integrity check, and status gating (`wolfCrypt_GetStatus_fips`). + +A stock wolfBoot build only addresses (1): it compiles individual `wolfcrypt/src/*.c` files selected by `SIGN`/`HASH`, with no POST or in-core integrity check. Building with `FIPS=1` (this page) addresses (2): wolfBoot links the wolfCrypt FIPS module boundary, runs the POST + in-core check at boot, and refuses to boot unless the module is operational. + +A production-validated deployment still requires the **licensed, validated** wolfCrypt FIPS bundle at the exact validated revision (not the evaluation "FIPS-ready" drop), the validated module version, and adherence to the module's Security Policy. Contact wolfSSL (facts@wolfssl.com) for the current certificate, validated module version, and integration guidance for a specific target. + +## Approved algorithms for image authentication + +wolfBoot authenticates images with a public-key signature over a hash of the image. The default wolfBoot signature algorithm, **ED25519, is NOT FIPS approved** and must not be used for a FIPS configuration. + +Approved pairs (select in the target `.config`): + +- Signature (`SIGN=`): `ECC256` / `ECC384` / `ECC521` (ECDSA P-256/P-384/P-521), or `RSAPSS2048` / `RSAPSS3072` / `RSAPSS4096` (RSA-PSS). +- Hash (`HASH=`): `SHA256`, `SHA384`. Match or exceed the signature strength (e.g. P-384 with SHA-384). +- Set `SPMATH=1` (the single-precision math backend the wolfCrypt FIPS module is validated with). + +Not approved for signing: `ED25519`, `ED448`. The post-quantum options (`LMS`/`XMSS`/`ML-DSA`) are governed by separate NIST standards and are out of scope here. + +## Getting the FIPS source + +Obtain a FIPS wolfCrypt source tree. For evaluation, the FIPS-ready bundle can be downloaded from wolfSSL: + +``` +https://www.wolfssl.com/wolfssl-5.9.2-gplv3-fips-ready.zip +``` + +Production use requires the licensed, validated FIPS bundle. Unpack it and point wolfBoot at it with `WOLFBOOT_LIB_WOLFSSL`. + +## Building wolfBoot with FIPS + +The `FIPS=1` build option (`options.mk`) rebuilds the wolfcrypt object list as the validated module boundary in link order (`wolfcrypt_first.o` first, `wolfcrypt_last.o` last, with `fips.o`/`fips_test.o` and the boundary crypto between them - the in-core integrity hash on GCC/ELF is enforced by this link order). Point the build at the FIPS tree and select an approved algorithm pair: + +``` +cp config/examples/sim-fips.config .config # or config/examples/cm4.config +make FIPS=1 WOLFBOOT_LIB_WOLFSSL=/path/to/wolfssl-5.9.2-gplv3-fips-ready \ + SIGN=ECC384 HASH=SHA384 SPMATH=1 +``` + +`-DHAVE_FIPS` is added by the `FIPS=1` block; `settings.h` in the FIPS tree defines the exact version (the FIPS-ready 5.9.2 bundle reports `HAVE_FIPS_VERSION 7`). The `HAVE_FIPS` block in `include/user_settings.h` enables the module's algorithm set, keeps the RNG/DRBG enabled, and wires the entropy seed (below). + +## Entropy source (required) + +The FIPS DRBG needs a seed. wolfBoot's lean configuration compiles out the OS seed paths, so a seed is provided via `CUSTOM_RAND_GENERATE_SEED` (the `HAVE_FIPS` block in `include/user_settings.h` keeps the RNG enabled by undoing wolfBoot's `WC_NO_RNG`/`WC_NO_HASHDRBG`). The example wiring points it at `wolfBoot_fips_seed()`, implemented per target: `/dev/urandom` on the simulator (`hal/sim.c`) and the BCM2711 RNG200 hardware TRNG on the CM4 (`hal/cm4.c`). Without a working seed, the ECDSA power-on self-test (which performs a sign) fails with `ECDSA_KAT_FIPS_E` because `wc_GenerateSeed()` returns `NOT_COMPILED_IN`. + +## Sealing the in-core integrity hash + +The module verifies an in-core integrity hash (HMAC-SHA-256 over the module's code and read-only data) at startup. A fresh build ships with a placeholder, so the first run reports a mismatch; capture the runtime hash and seal it: + +1. Build and run with a FIPS callback registered (wolfBoot does this in `src/loader.c`). On a mismatch the module reports the runtime hash; wolfBoot prints it (`FIPS in-core hash = ...`, from `wolfCrypt_GetCoreHash_fips()`), and on the CM4 the test app (`test-app/app_cm4.c`) prints it over UART. +2. Copy the reported 64-hex-character hash into `verifyCore[]` in `wolfcrypt/src/fips_test.c`. +3. Rebuild and re-run. `wolfCrypt_GetStatus_fips()` now returns 0 (operational). + +The seal is **specific to the exact binary layout**: any code change that shifts the FIPS module's link addresses changes the in-core hash and requires a re-seal. Re-sealing `verifyCore[]` itself does not shift addresses (same-size rewrite), so once the rest of the build is fixed the seal converges in one pass. + +## Bare-metal targets + +The FIPS module targets a hosted environment; a few things must be provided on bare-metal (the CM4 does all of these): + +- **POST entry.** The module registers its POST via a C constructor (`.init_array`), which a hosted runtime runs before `main()`. wolfBoot's bare-metal startup does not run `.init_array`, so build with `NO_ATTRIBUTE_CONSTRUCTOR` and call `fipsEntry()` explicitly (`src/loader.c`). +- **Normal (cacheable) memory.** wolfBoot's simple startup runs with the MMU off, where all memory is Device-nGnRnE and unaligned / 128-bit SIMD accesses fault (the FIPS module and newlib `printf`/`snprintf` do both). The CM4 HAL enables a minimal identity MMU with DDR mapped Normal cacheable before the POST (`cm4_mmu_enable`), and tears it down (clean D-cache, disable MMU/caches) before the boot handoff (`cm4_mmu_disable`) so the loaded image is coherent and the application starts MMU-off. +- **libc.** The module uses malloc/printf; stub the newlib syscalls (`--specs=nosys.specs`) and provide a bounded `_sbrk` so the heap cannot grow into the unverified image (the CM4 HAL allocates from a fixed static buffer in `hal/cm4.c`). + +Bring the module up on the simulator (`config/examples/sim-fips.config`) first - it exercises the whole flow (module boundary, POST, in-core seal, verify, A/B update) with no hardware. + +## Verifying operation + +- POST/CASTs run at module initialization; `wc_RunAllCast_fips()` runs the conditional algorithm self-tests and `wolfCrypt_GetStatus_fips()` reports the module status (0 = operational). +- wolfBoot treats a non-zero FIPS status as a hard failure and refuses to boot (`src/loader.c`). +- A deliberately corrupted module boundary (flip a byte) makes the in-core check fail and blocks the boot - the negative test for the integration. + +## See also + +- [Targets.md](Targets.md) - Raspberry Pi Compute Module 4 (BCM2711) target. FIPS 140-3 authenticated boot (module operational -> SHA-384 integrity -> ECDSA-P384 verify seeded by the BCM2711 hardware TRNG -> handoff) is validated on CM4 hardware. diff --git a/docs/README.md b/docs/README.md index d86720d9c7..cbe7a1f33a 100644 --- a/docs/README.md +++ b/docs/README.md @@ -11,6 +11,7 @@ See also: [wolfBoot Product Overview](https://www.wolfssl.com/products/wolfboot/ - [**encrypted_partitions.md**](./encrypted_partitions.md) - Creating and managing encrypted firmware/data partitions. - [**firmware_image.md**](./firmware_image.md) - wolfBoot firmware image format, layout, and metadata. - [**firmware_update.md**](./firmware_update.md) - Update flow: slots, verification, rollback, and recovery. +- [**FIPS.md**](./FIPS.md) - Building wolfBoot with the wolfCrypt FIPS 140-3 module: approved algorithms, DRBG entropy, and in-core integrity sealing. - [**flash-OTP.md**](./flash-OTP.md) - Using One-Time Programmable (OTP) regions in flash for secure data. - [**flash_partitions.md**](./flash_partitions.md) - Flash partitioning schemes and configuration guidance. - [**HAL.md**](./HAL.md) - Hardware Abstraction Layer notes and porting considerations. diff --git a/docs/Targets.md b/docs/Targets.md index 635cd5dad0..052aaa0dd5 100644 --- a/docs/Targets.md +++ b/docs/Targets.md @@ -3767,7 +3767,7 @@ Booting at 0x3080000 ### FIPS 140-3 -The CM4 target uses `SIGN=ECC384 HASH=SHA384` (FIPS-approved) and can perform its signature verification with the wolfCrypt FIPS 140-3 validated module. The on-target harness in `test-app/app_cm4.c` registers a FIPS callback and prints the runtime in-core integrity hash over the UART for the `verifyCore[]` bootstrap. See [FIPS.md](FIPS.md) for the full build and hash-sealing procedure. +The CM4 target uses `SIGN=ECC384 HASH=SHA384` (FIPS-approved) and can perform its signature verification with the wolfCrypt FIPS 140-3 module (build `config/examples/cm4.config` with `FIPS=1`, pointing `WOLFBOOT_LIB_WOLFSSL` at a FIPS wolfSSL tree). At boot the module runs its power-on self-test and in-core integrity check, and wolfBoot refuses to boot unless the module is operational. Entropy for the FIPS DRBG comes from the BCM2711 RNG200 hardware TRNG. The full flow has been brought up and exercised end to end on CM4 hardware using the FIPS-ready bundle: FIPS module operational -> SHA-384 integrity -> ECDSA-P384 signature verification -> boot handoff. A production, CMVP-validated deployment additionally requires the licensed validated wolfCrypt FIPS bundle at the validated revision (see [FIPS.md](FIPS.md)). The on-target harness in `test-app/app_cm4.c` prints the runtime in-core hash over the UART for the `verifyCore[]` seal. See [FIPS.md](FIPS.md) for the full build, entropy, and hash-sealing procedure. ## Xilinx Zynq UltraScale diff --git a/hal/cm4.c b/hal/cm4.c index 2a041ff051..d37b94a88d 100644 --- a/hal/cm4.c +++ b/hal/cm4.c @@ -42,6 +42,11 @@ /* Fixed addresses (provided by the linker script) */ extern void *kernel_addr, *update_addr, *dts_addr; +#if defined(HAVE_FIPS) +void cm4_mmu_enable(void); /* defined below; called from hal_init */ +void cm4_mmu_disable(void); /* defined below; called from hal_prepare_boot */ +#endif + #if defined(DEBUG_UART) static void uart_tx(char c) { @@ -129,13 +134,175 @@ void hal_init(void) wolfBoot_printf("wolfBoot CM4 (BCM2711 Cortex-A72) hal_init, EL%d\n", (int)((el >> 2) & 0x3)); #endif +#if defined(HAVE_FIPS) + /* Bring up Normal cacheable memory before the FIPS POST, which uses + * unaligned / SIMD accesses that the MMU-off Device memory rejects. */ + cm4_mmu_enable(); +#endif } void hal_prepare_boot(void) { +#if defined(HAVE_FIPS) + /* Undo cm4_mmu_enable() before handoff: flush the app out of the D-cache + * and return to the MMU-off state the application expects. */ + cm4_mmu_disable(); +#endif } #if defined(HAVE_FIPS) +/* Bounded heap for the FIPS module's malloc. wolfBoot builds the FIPS target + * with --specs=nosys.specs, whose newlib _sbrk grows unbounded from the linker + * 'end' symbol - toward the unverified image staged at kernel_addr (0x140000). + * Provide our own _sbrk over a fixed static buffer (in .bss, well below the + * image) so heap growth is bounded and can never reach kernel_addr. */ +#ifndef CM4_FIPS_HEAP_SIZE +#define CM4_FIPS_HEAP_SIZE (128 * 1024) +#endif +static unsigned char cm4_fips_heap[CM4_FIPS_HEAP_SIZE]; +void* _sbrk(int incr); +void* _sbrk(int incr) +{ + static unsigned char* brk = cm4_fips_heap; + unsigned char* prev = brk; + + if (incr < 0) + return (void*)-1; + if ((size_t)(brk - cm4_fips_heap) + (size_t)incr > sizeof(cm4_fips_heap)) + return (void*)-1; /* out of heap */ + brk += incr; + return (void*)prev; +} + +/* Minimal identity-mapped MMU + caches for the CM4. wolfBoot's simple startup + * runs with the MMU off, so all memory is Device-nGnRnE, which faults on the + * unaligned / 128-bit SIMD accesses the FIPS module and newlib printf perform. + * Mapping DDR as Normal (cacheable) permits those accesses and speeds up the + * crypto; the peripheral region (incl. 0xFE000000) stays Device. + * Four 1GB block descriptors cover the 32-bit VA space at translation level 1. */ +#define MMU_BLOCK_NORMAL 0x0000000000000701ULL /* block, AttrIdx0, AF, SH inner */ +#define MMU_BLOCK_DEVICE 0x0000000000000405ULL /* block, AttrIdx1, AF, SH none */ + +static volatile uint64_t cm4_l1_table[512] __attribute__((aligned(4096))); + +/* Data-cache maintenance by set/way over all levels to the point of coherency. + * clean != 0 -> clean+invalidate (dc cisw); else invalidate-only (dc isw). */ +static void cm4_dcache_maint(int clean) +{ + uint64_t clidr, ccsidr; + unsigned int level, loc, ctype, linesize, ways, sets, way, set, wayshift; + + __asm__ volatile("dsb sy"); + __asm__ volatile("mrs %0, clidr_el1" : "=r"(clidr)); + loc = (unsigned int)((clidr >> 24) & 0x7); /* Level of Coherency */ + for (level = 0; level < loc; level++) { + ctype = (unsigned int)((clidr >> (level * 3)) & 0x7); + if (ctype < 2) /* no data/unified cache at this level */ + continue; + __asm__ volatile("msr csselr_el1, %0" :: "r"((uint64_t)(level << 1))); + __asm__ volatile("isb"); + __asm__ volatile("mrs %0, ccsidr_el1" : "=r"(ccsidr)); + linesize = (unsigned int)(ccsidr & 0x7) + 4; /* log2(bytes) */ + ways = (unsigned int)((ccsidr >> 3) & 0x3FF); /* assoc - 1 */ + sets = (unsigned int)((ccsidr >> 13) & 0x7FFF); /* sets - 1 */ + /* __builtin_clz(0) is UB; a direct-mapped cache (ways==0) never uses + * the way field (way stays 0), so the shift amount is irrelevant. */ + wayshift = (ways == 0) ? 32u : (unsigned int)__builtin_clz(ways); + for (set = 0; set <= sets; set++) { + for (way = 0; way <= ways; way++) { + uint64_t val = ((uint64_t)(level << 1)) + | ((uint64_t)way << wayshift) + | ((uint64_t)set << linesize); + if (clean) + __asm__ volatile("dc cisw, %0" :: "r"(val)); + else + __asm__ volatile("dc isw, %0" :: "r"(val)); + } + } + } + __asm__ volatile("dsb sy"); + __asm__ volatile("isb"); +} + +void cm4_mmu_enable(void) +{ + unsigned long sctlr; + int i; + + /* 0-3GB DDR -> Normal; 3-4GB peripherals (0xFE000000) -> Device. */ + for (i = 0; i < 4; i++) { + uint64_t base = (uint64_t)i << 30; + cm4_l1_table[i] = base | ((i == 3) ? MMU_BLOCK_DEVICE : MMU_BLOCK_NORMAL); + } + /* MAIR: Attr0 = 0xFF Normal WB write-alloc, Attr1 = 0x00 Device-nGnRnE. */ + __asm__ volatile("msr mair_el2, %0" :: "r"(0x00000000000000FFUL)); + __asm__ volatile("msr ttbr0_el2, %0" + :: "r"((uint64_t)(uintptr_t)cm4_l1_table)); + /* TCR_EL2: T0SZ=32 (32-bit VA), 4KB granule, WB cacheable inner-shareable + * table walks, 36-bit PA. */ + __asm__ volatile("msr tcr_el2, %0" :: "r"(0x0000000000013520UL)); + __asm__ volatile("isb"); + __asm__ volatile("tlbi alle2"); + __asm__ volatile("dsb sy"); + /* Invalidate the D-cache (and I-cache) before enabling them, so no stale + * lines left by an earlier boot stage surface once caching is on. */ + cm4_dcache_maint(0); + __asm__ volatile("ic iallu"); + __asm__ volatile("dsb sy"); + __asm__ volatile("isb"); + /* SCTLR_EL2: enable MMU (M), data cache (C), instruction cache (I). */ + __asm__ volatile("mrs %0, sctlr_el2" : "=r"(sctlr)); + sctlr |= (1UL << 0) | (1UL << 2) | (1UL << 12); + __asm__ volatile("msr sctlr_el2, %0" :: "r"(sctlr)); + __asm__ volatile("isb"); +} + +/* Tear down the MMU/caches before boot handoff: clean the freshly-copied app + * out of the D-cache to memory, disable the MMU and caches, and invalidate the + * I-cache/TLB. Returns the CPU to the MMU-off state the application (and the + * ARM64 Linux boot protocol) expects. */ +void cm4_mmu_disable(void) +{ + unsigned long sctlr; + + cm4_dcache_maint(1); /* clean+invalidate: flush the loaded app to memory */ + __asm__ volatile("mrs %0, sctlr_el2" : "=r"(sctlr)); + sctlr &= ~((1UL << 0) | (1UL << 2) | (1UL << 12)); /* clear M, C, I */ + __asm__ volatile("msr sctlr_el2, %0" :: "r"(sctlr)); + __asm__ volatile("isb"); + __asm__ volatile("ic iallu"); + __asm__ volatile("tlbi alle2"); + __asm__ volatile("dsb sy"); + __asm__ volatile("isb"); +} +#endif /* HAVE_FIPS */ + +#if defined(DEBUG) && defined(DEBUG_UART) +/* CM4 bring-up diagnostic: exception handler invoked from cm4_vectors in + * src/boot_aarch64_start.S. Dumps the fault syndrome so a data/instruction + * abort shows up over UART instead of hanging silently. Built only with + * DEBUG + DEBUG_UART. ESR_EL2[31:26] = exception class. */ +void cm4_fault_handler(unsigned long esr, unsigned long elr, unsigned long far); +void cm4_fault_handler(unsigned long esr, unsigned long elr, unsigned long far) +{ + wolfBoot_printf("\n*** CM4 EXCEPTION ***\n"); + wolfBoot_printf("ESR_EL2=0x%08x EC=0x%02x\n", + (unsigned)esr, (unsigned)((esr >> 26) & 0x3F)); + wolfBoot_printf("ELR_EL2=0x%08x%08x\n", + (unsigned)(elr >> 32), (unsigned)elr); + wolfBoot_printf("FAR_EL2=0x%08x%08x\n", + (unsigned)(far >> 32), (unsigned)far); +} +#endif /* DEBUG && DEBUG_UART */ + +#if defined(HAVE_FIPS) +/* Upper bound on the busy-wait for the RNG200 FIFO to fill. This is a coarse, + * A72-clock-dependent spin count (not a wall-clock timeout); it only guards + * against a wedged RNG so the seed read cannot hang forever. Tune if needed. */ +#ifndef RNG200_FIFO_WAIT_ITERS +#define RNG200_FIFO_WAIT_ITERS 200000000U +#endif + /* FIPS DRBG entropy seed from the BCM2711 RNG200 hardware TRNG. Registered via * CUSTOM_RAND_GENERATE_SEED in include/user_settings.h. The RNG200 has NIST * SP800-90B startup/continuous health tests in hardware. */ @@ -163,7 +330,7 @@ int wolfBoot_fips_seed(unsigned char* output, unsigned int sz) /* wait for at least one 32-bit word in the FIFO (bounded) */ guard = 0; while ((*RNG_FIFO_COUNT & 0xFF) == 0) { - if (++guard > 200000000U) { + if (++guard > RNG200_FIFO_WAIT_ITERS) { #if defined(DEBUG_UART) wolfBoot_printf("RNG200 FIFO timeout int=0x%08x ctrl=0x%08x\n", (unsigned)*RNG_INT_STATUS, (unsigned)*RNG_CTRL); @@ -176,18 +343,6 @@ int wolfBoot_fips_seed(unsigned char* output, unsigned int sz) for (i = 0; i < n; i++) output[pos++] = (unsigned char)(word >> (i * 8)); } - -#if defined(DEBUG_UART) - { - static int traced = 0; - if (!traced) { - wolfBoot_printf("RNG200 seed %02x %02x %02x %02x %02x %02x %02x %02x\n", - output[0], output[1], output[2], output[3], - output[4], output[5], output[6], output[7]); - traced = 1; - } - } -#endif return 0; } #endif /* HAVE_FIPS */ @@ -304,11 +459,16 @@ void sdhci_platform_set_bus_mode(int is_emmc) * Falls back to the BCM2711 system counter frequency if CNTFRQ_EL0 is 0. */ uint64_t hal_get_timer_us(void) { +#if defined(__aarch64__) uint64_t count, freq; __asm__ volatile("mrs %0, CNTPCT_EL0" : "=r"(count)); __asm__ volatile("mrs %0, CNTFRQ_EL0" : "=r"(freq)); if (freq == 0) freq = BCM2711_TIMER_CLK_FREQ; return (uint64_t)(((__uint128_t)count * 1000000ULL) / freq); +#else + /* Non-AArch64 host build (unit tests): the generic timer is unavailable. */ + return 0; +#endif } #endif /* DISK_SDCARD || DISK_EMMC */ diff --git a/hal/cm4.h b/hal/cm4.h index 7b5d650364..6bdf60027b 100644 --- a/hal/cm4.h +++ b/hal/cm4.h @@ -36,7 +36,10 @@ #define BCM2711_MMIO_BASE 0xFE000000 #define BCM2711_GPIO_BASE (BCM2711_MMIO_BASE + 0x200000) #define BCM2711_UART0_BASE (BCM2711_GPIO_BASE + 0x1000) /* PL011 */ +/* Overridable so host unit tests can retarget the SDHCI glue at a mock buffer */ +#ifndef BCM2711_EMMC2_BASE #define BCM2711_EMMC2_BASE (BCM2711_MMIO_BASE + 0x340000) /* Arasan SDHCI */ +#endif #define BCM2711_RNG_BASE (BCM2711_MMIO_BASE + 0x104000) /* RNG200 TRNG */ /* RNG200 (iproc-rng200) register offsets */ diff --git a/hal/sim.c b/hal/sim.c index 63bf96d92f..6393e07e25 100644 --- a/hal/sim.c +++ b/hal/sim.c @@ -122,6 +122,34 @@ static int sim_cryptocb(int devIdArg, wc_CryptoInfo* info, void* ctx) #include "port/posix/posix_flash_file.h" #endif /* WOLFBOOT_ENABLE_WOLFHSM_SERVER */ +#if defined(HAVE_FIPS) +/* FIPS DRBG entropy seed for the simulator: read from /dev/urandom. + * Registered via CUSTOM_RAND_GENERATE_SEED in include/user_settings.h. */ +int wolfBoot_fips_seed(unsigned char* output, unsigned int sz) +{ + unsigned int pos = 0; + int fd = open("/dev/urandom", O_RDONLY); + if (fd < 0) + return -1; + while (pos < sz) { + ssize_t r = read(fd, output + pos, sz - pos); + if (r < 0) { + if (errno == EINTR) + continue; /* interrupted, retry */ + close(fd); + return -1; + } + if (r == 0) { /* unexpected EOF on /dev/urandom */ + close(fd); + return -1; + } + pos += (unsigned int)r; + } + close(fd); + return 0; +} +#endif /* HAVE_FIPS */ + /* Global pointer to the internal and external flash base */ uint8_t *sim_ram_base; static uint8_t *flash_base; diff --git a/include/user_settings.h b/include/user_settings.h index 5c59ae3ed1..d4a6075e63 100644 --- a/include/user_settings.h +++ b/include/user_settings.h @@ -43,6 +43,53 @@ #define HAVE_EMPTY_AGGREGATES 0 #define HAVE_ANONYMOUS_INLINE_AGGREGATES 0 +#ifdef HAVE_FIPS + /* wolfCrypt FIPS 140-3 module boundary algorithm set. FIPS requires the + * whole validated module (all approved algorithms) to be present so the + * power-on self-tests and in-core integrity check operate. See + * docs/FIPS.md. Enabled via FIPS=1 (-DHAVE_FIPS in options.mk). */ + #define WOLFSSL_FIPS_READY + /* Single-threaded: the FIPS POST runs at init before any other access, so + * the module's thread-local state is a plain global (no pthread TLS). */ + #define NO_THREAD_LS + /* wolfBoot's bare-metal startup does not run C constructors (.init_array), + * so the FIPS module's power-on self-test entry (fipsEntry) must be a + * normal callable function that wolfBoot invokes explicitly at startup. */ + #define NO_ATTRIBUTE_CONSTRUCTOR + #define WOLFSSL_BASE16 /* fips_test.c hash hex encode/decode */ + #define WOLFSSL_BASE64_ENCODE + #define WOLFSSL_SHA224 + #define WOLFSSL_SHA384 + #define WOLFSSL_SHA512 + #define WOLFSSL_SHA3 + #define HAVE_AESGCM + #define HAVE_AESCCM + #define HAVE_AES_ECB /* AES CAST uses wc_AesEcbEncrypt */ + #define HAVE_AES_CBC /* AES-CBC CAST */ + #define WOLFSSL_AES_COUNTER + #define WOLFSSL_AES_DIRECT + #define WOLFSSL_AES_CFB + #define WOLFSSL_AES_OFB + #define WOLFSSL_AES_XTS + #define WOLFSSL_CMAC + #define HAVE_HKDF + #define HAVE_ECC + #define WOLFSSL_ECDSA_SET_K + #define WOLFSSL_VALIDATE_ECC_IMPORT + #define WOLFSSL_VALIDATE_ECC_KEYGEN + #define WOLFSSL_KEY_GEN + #define WOLFSSL_PUBLIC_MP + #define WOLFSSL_SP_MATH_ALL + /* FIPS DRBG entropy seed source. The RNG must NOT be disabled in FIPS mode + * (see the undef block below which removes WC_NO_RNG/WC_NO_HASHDRBG). The + * seed comes from a HAL-provided source: /dev/urandom on sim, the BCM2711 + * RNG200 hardware TRNG on CM4. */ + #if defined(ARCH_SIM) || defined(TARGET_cm4) + #define CUSTOM_RAND_GENERATE_SEED wolfBoot_fips_seed + extern int wolfBoot_fips_seed(unsigned char* output, unsigned int sz); + #endif +#endif /* HAVE_FIPS */ + /* Stdlib Types */ #define CTYPE_USER /* don't let wolfCrypt types.h include ctype.h */ @@ -195,7 +242,7 @@ extern int tolower(int c); !defined(WOLFCRYPT_TEST) && !defined(WOLFCRYPT_BENCHMARK) && \ !defined(WOLFBOOT_ENABLE_WOLFHSM_CLIENT) && \ !defined(WOLFBOOT_ENABLE_WOLFHSM_SERVER) -# if !defined(WOLFBOOT_TPM) +# if !defined(WOLFBOOT_TPM) && !defined(HAVE_FIPS) # define NO_ECC_SIGN # define NO_ECC_DHE /* For Renesas RX do not enable the misc.c constant time code @@ -434,10 +481,12 @@ extern int tolower(int c); # endif #endif -/* Drop SHA-256 when neither the image hash nor any other user needs it */ +/* Drop SHA-256 when neither the image hash nor any other user needs it. + * FIPS keeps SHA-256: the module's in-core integrity check is HMAC-SHA-256. */ #if (defined(WOLFBOOT_HASH_SHA384) || defined(WOLFBOOT_HASH_SHA3_384)) && \ !defined(WOLFBOOT_ENABLE_HASH_SHA256) && defined(NO_RSA) && \ !defined(WOLFBOOT_TPM) && !defined(WOLFCRYPT_SECURE_MODE) && \ + !defined(HAVE_FIPS) && \ !defined(WOLFCRYPT_TEST) && !defined(WOLFCRYPT_BENCHMARK) # define NO_SHA256 #endif @@ -589,7 +638,8 @@ extern int tolower(int c); #endif #if !defined(WOLFCRYPT_SECURE_MODE) && !defined(WOLFBOOT_TPM_PARMENC) && \ - !defined(WOLFCRYPT_TEST) && !defined(WOLFCRYPT_BENCHMARK) + !defined(WOLFCRYPT_TEST) && !defined(WOLFCRYPT_BENCHMARK) && \ + !defined(HAVE_FIPS) #if !(defined(WOLFBOOT_ENABLE_WOLFHSM_CLIENT) && \ defined(WOLFBOOT_SIGN_ML_DSA)) && \ !defined(WOLFBOOT_ENABLE_WOLFHSM_SERVER) @@ -636,7 +686,8 @@ extern int tolower(int c); #if !defined(ENCRYPT_WITH_AES128) && !defined(ENCRYPT_WITH_AES256) && \ !defined(WOLFBOOT_TPM_PARMENC) && !defined(WOLFCRYPT_SECURE_MODE) && \ !defined(SECURE_PKCS11) && !defined(WOLFCRYPT_TZ_PSA) && \ - !defined(WOLFCRYPT_TEST) && !defined(WOLFCRYPT_BENCHMARK) + !defined(WOLFCRYPT_TEST) && !defined(WOLFCRYPT_BENCHMARK) && \ + !defined(HAVE_FIPS) #define NO_AES #endif @@ -699,6 +750,25 @@ extern int tolower(int c); #define NO_CHECK_PRIVATE_KEY #define NO_KDF +#ifdef HAVE_FIPS + /* The FIPS validated module requires its whole boundary present; undo the + * lean verify-only disables above so the module's approved algorithms and + * their power-on self-tests operate (see docs/FIPS.md). */ + #undef NO_HMAC + #undef NO_CMAC + #undef NO_SHA + #undef NO_KDF + #undef NO_ASN + #undef NO_DEV_RANDOM + #undef NO_ECC_KEY_EXPORT + #undef WC_NO_RNG + #undef WC_NO_HASHDRBG + #undef NO_PWDBASED + #undef NO_CODING + #undef NO_AES_CBC /* FIPS AES-CBC CAST needs CBC mode */ + #define HAVE_PBKDF2 +#endif /* HAVE_FIPS */ + /* wolfCrypt Test/Benchmark Configuration */ #ifdef WOLFCRYPT_TEST /* Skip extended tests to save memory */ diff --git a/options.mk b/options.mk index c3d6b75bd6..53c525c5c9 100644 --- a/options.mk +++ b/options.mk @@ -1835,3 +1835,48 @@ endif # includers (test-app), where a self-referencing += would not terminate. AUX_WOLFCRYPT_OBJS_NEW:=$(filter-out $(WOLFCRYPT_OBJS),$(sort $(AUX_WOLFCRYPT_OBJS))) WOLFCRYPT_OBJS+=$(AUX_WOLFCRYPT_OBJS_NEW) +# --------------------------------------------------------------------------- +# wolfCrypt FIPS 140-3 module (FIPS=1) +# +# Point WOLFBOOT_LIB_WOLFSSL at an unpacked FIPS / FIPS-ready wolfSSL tree. +# The in-core integrity hash on GCC/ELF is enforced by LINK ORDER: +# wolfcrypt_first.o must be first and wolfcrypt_last.o last, with the FIPS +# boundary (crypto + fips.o + fips_test.o) between them. We therefore rebuild +# WOLFCRYPT_OBJS from scratch in that order, replacing the piecemeal per-SIGN +# selection above (the SIGN/HASH CFLAGS remain in effect). See docs/FIPS.md. +ifeq ($(FIPS),1) + CFLAGS+=-DHAVE_FIPS + # The FIPS module pulls in libc malloc/printf. On bare-metal targets stub the + # newlib syscalls with nosys.specs; the HAL provides a bounded _sbrk so the + # heap cannot grow into the unverified image (see hal/cm4.c). + ifneq ($(ARCH),sim) + LDFLAGS += --specs=nosys.specs + endif + WCDIR=$(WOLFBOOT_LIB_WOLFSSL)/wolfcrypt/src + WOLFCRYPT_OBJS := \ + $(WCDIR)/wolfcrypt_first.o \ + $(WCDIR)/hash.o \ + $(WCDIR)/hmac.o \ + $(WCDIR)/kdf.o \ + $(WCDIR)/pwdbased.o \ + $(WCDIR)/random.o \ + $(WCDIR)/sha.o \ + $(WCDIR)/sha256.o \ + $(WCDIR)/sha512.o \ + $(WCDIR)/sha3.o \ + $(WCDIR)/aes.o \ + $(WCDIR)/cmac.o \ + $(WCDIR)/ecc.o \ + $(WCDIR)/sp_int.o \ + $(WCDIR)/wolfmath.o \ + $(WCDIR)/memory.o \ + $(WCDIR)/wc_port.o \ + $(WCDIR)/logging.o \ + $(WCDIR)/error.o \ + $(WCDIR)/coding.o \ + $(WCDIR)/asn.o \ + $(WCDIR)/wc_encrypt.o \ + $(WCDIR)/fips.o \ + $(WCDIR)/fips_test.o \ + $(WCDIR)/wolfcrypt_last.o +endif diff --git a/src/boot_aarch64_start.S b/src/boot_aarch64_start.S index d3de26a131..1157a0eeec 100644 --- a/src/boot_aarch64_start.S +++ b/src/boot_aarch64_start.S @@ -1176,6 +1176,11 @@ _vector_table: // EL == 2? mov x2, #3 << 20 msr cptr_el2, x2 /* Enable FP/SIMD */ +#if defined(TARGET_cm4) && defined(DEBUG) && defined(DEBUG_UART) + ldr x2, =cm4_vectors /* install fault-dump exception vectors (debug) */ + msr VBAR_EL2, x2 + isb /* ensure new vector base is in effect */ +#endif b 0f 1: mov x0, #3 << 20 @@ -1192,6 +1197,45 @@ _vector_table: 8: mov sp, x1 // set stack pointer bl boot_entry_C // boot_entry_C never returns b 7b // go to sleep anyhow in case. + +#if defined(TARGET_cm4) && defined(DEBUG) && defined(DEBUG_UART) +/* Minimal EL2 exception vectors for CM4 bring-up debug. On any exception + * (data/instruction abort, etc.) dump ESR/ELR/FAR over UART instead of the + * silent hang the simple startup would otherwise produce. */ +.macro CM4_VEC label + .align 7 +\label: + b cm4_fault_common +.endm + +.align 11 +.global cm4_vectors +cm4_vectors: + CM4_VEC cm4_v0 /* Current EL, SP0: Sync */ + CM4_VEC cm4_v1 /* IRQ */ + CM4_VEC cm4_v2 /* FIQ */ + CM4_VEC cm4_v3 /* SError */ + CM4_VEC cm4_v4 /* Current EL, SPx: Sync */ + CM4_VEC cm4_v5 /* IRQ */ + CM4_VEC cm4_v6 /* FIQ */ + CM4_VEC cm4_v7 /* SError */ + CM4_VEC cm4_v8 /* Lower EL, AArch64: Sync */ + CM4_VEC cm4_v9 /* IRQ */ + CM4_VEC cm4_v10 /* FIQ */ + CM4_VEC cm4_v11 /* SError */ + CM4_VEC cm4_v12 /* Lower EL, AArch32: Sync */ + CM4_VEC cm4_v13 /* IRQ */ + CM4_VEC cm4_v14 /* FIQ */ + CM4_VEC cm4_v15 /* SError */ + +cm4_fault_common: + mrs x0, esr_el2 + mrs x1, elr_el2 + mrs x2, far_el2 + bl cm4_fault_handler /* void cm4_fault_handler(esr, elr, far) */ +9: wfi + b 9b +#endif /* TARGET_cm4 && DEBUG && DEBUG_UART */ #if 0 .section ".boot" .global _vector_table diff --git a/src/loader.c b/src/loader.c index 3c26f4db42..211b58cf93 100644 --- a/src/loader.c +++ b/src/loader.c @@ -58,6 +58,22 @@ static volatile const uint32_t __attribute__((used)) wolfboot_version = WOLFBOOT extern void (** const IV_RAM)(void); #endif +#ifdef HAVE_FIPS +#include "printf.h" +#include +/* FIPS module power-on self-test entry. With NO_ATTRIBUTE_CONSTRUCTOR it is a + * plain function (not an .init_array constructor) that wolfBoot calls at boot. */ +extern void fipsEntry(void); +/* wolfCrypt FIPS in-core integrity / CAST callback. On a hash mismatch + * (IN_CORE_FIPS_E) the module reports the runtime hash here; copy it into + * verifyCore[] in wolfcrypt/src/fips_test.c and rebuild (see docs/FIPS.md). */ +static void wolfBoot_fipsCb(int ok, int err, const char* hash) +{ + wolfBoot_printf("FIPS callback: ok=%d err=%d\n", ok, err); + wolfBoot_printf("hash = %s\n", hash != NULL ? hash : "(null)"); +} +#endif + #ifdef TARGET_sim /** * @brief Command line arguments for the test-app in sim mode. @@ -106,6 +122,21 @@ int main(void) wolfBoot_hook_preinit(); #endif hal_init(); +#ifdef HAVE_FIPS + /* Run the FIPS power-on self-test (in-core integrity + CASTs) and refuse + * to boot unless the module is operational. See docs/FIPS.md. */ + wolfCrypt_SetCb_fips(wolfBoot_fipsCb); + fipsEntry(); + if (wolfCrypt_GetStatus_fips() != 0) { + wolfBoot_printf("FIPS 140-3 module NOT operational (status=%d); halting\n", + wolfCrypt_GetStatus_fips()); + /* On self-test failure this returns the runtime in-core hash to seal + * into verifyCore[] in fips_test.c. */ + wolfBoot_printf("FIPS in-core hash = %s\n", wolfCrypt_GetCoreHash_fips()); + wolfBoot_panic(); + } + wolfBoot_printf("FIPS 140-3 module operational\n"); +#endif #ifdef TEST_FLASH hal_flash_test(); #endif diff --git a/test-app/app_cm4.c b/test-app/app_cm4.c index 865479cd8f..4c1232e355 100644 --- a/test-app/app_cm4.c +++ b/test-app/app_cm4.c @@ -69,12 +69,12 @@ static void uart_putdec(int v) unsigned int u; int i = 0; + /* Negate in the unsigned domain: -(unsigned)INT_MIN is well defined, + * unlike negating the signed int (UB for INT_MIN). */ + u = (unsigned int)v; if (v < 0) { uart_putc('-'); - u = (unsigned int)(-v); - } - else { - u = (unsigned int)v; + u = (unsigned int)(-u); } do { buf[i++] = (char)('0' + (u % 10)); diff --git a/tools/unit-tests/Makefile b/tools/unit-tests/Makefile index 3a1b466086..52e5300624 100644 --- a/tools/unit-tests/Makefile +++ b/tools/unit-tests/Makefile @@ -60,7 +60,7 @@ TESTS:=unit-parser unit-fdt unit-extflash unit-string unit-spi-flash unit-aes128 unit-update-disk unit-update-disk-oob unit-multiboot unit-boot-x86-fsp unit-loader-tpm-init unit-qspi-flash unit-fwtpm-stub unit-tpm-rsa-exp \ unit-image-nopart unit-image-sha384 unit-image-sha3-384 unit-store-sbrk \ unit-tpm-blob unit-policy-create unit-policy-sign unit-rot-auth unit-sdhci-response-bits \ - unit-sdhci-disk-unaligned unit-sign-encrypted-output \ + unit-sdhci-disk-unaligned unit-cm4-sdhci unit-sign-encrypted-output \ unit-keygen-xmss-params TESTS+=unit-tpm-check-rot-auth TESTS+=unit-tpm-api-names @@ -407,6 +407,10 @@ unit-sdhci-disk-unaligned: ../../include/target.h unit-sdhci-disk-unaligned.c gcc -o $@ $^ $(CFLAGS) -ffunction-sections -fdata-sections $(LDFLAGS) \ -Wl,--gc-sections +unit-cm4-sdhci: ../../include/target.h unit-cm4-sdhci.c + gcc -o $@ $^ $(CFLAGS) -I../.. -ffunction-sections -fdata-sections $(LDFLAGS) \ + -Wl,--gc-sections + unit-aes128: ../../include/target.h unit-extflash.c gcc -o $@ $^ $(CFLAGS) $(LDFLAGS) diff --git a/tools/unit-tests/unit-cm4-sdhci.c b/tools/unit-tests/unit-cm4-sdhci.c new file mode 100644 index 0000000000..fd300822a5 --- /dev/null +++ b/tools/unit-tests/unit-cm4-sdhci.c @@ -0,0 +1,162 @@ +/* unit-cm4-sdhci.c + * + * Unit tests for the CM4 (BCM2711 EMMC2) SDHCI register-translation glue in + * hal/cm4.c: sdhci_reg_read/sdhci_reg_write translate the generic driver's + * Cadence-style SRS offsets to the standard Arasan SDHCI layout. + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfBoot. + * + * wolfBoot is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfBoot is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include +#include +#include + +/* 256-byte mock of the EMMC2 standard SDHCI register window. Retarget the CM4 + * HAL's EMMC2 base at it so sdhci_reg_read/write hit host memory, not MMIO. */ +static uint8_t cm4_mock_emmc[0x100]; +#define BCM2711_EMMC2_BASE ((uintptr_t)cm4_mock_emmc) + +/* Compile the CM4 SDHCI glue for the host: pull in only the DISK_SDCARD block. */ +#define ARCH_AARCH64 +#define DISK_SDCARD 1 + +#include "../../hal/cm4.c" + +/* Cadence SRS offset the generic driver uses (0x200 + std). */ +#define SRS(n) (CADENCE_SRS_OFFSET + (n)) + +static void clear_mock(void) +{ + memset(cm4_mock_emmc, 0, sizeof(cm4_mock_emmc)); +} + +/* SRS10 (std 0x28) write is decomposed into four 8-bit registers. */ +START_TEST(test_srs10_byte_decomposition) +{ + clear_mock(); + sdhci_reg_write(SRS(0x28), 0x44332211); + ck_assert_uint_eq(cm4_mock_emmc[STD_SDHCI_HOST_CTRL1], 0x11); + ck_assert_uint_eq(cm4_mock_emmc[STD_SDHCI_POWER_CTRL], 0x22); + ck_assert_uint_eq(cm4_mock_emmc[STD_SDHCI_BLKGAP_CTRL], 0x33); + ck_assert_uint_eq(cm4_mock_emmc[STD_SDHCI_WAKEUP_CTRL], 0x44); +} +END_TEST + +/* SRS11 (std 0x2C) write is a 16-bit clock reg + two 8-bit regs. */ +START_TEST(test_srs11_split) +{ + uint16_t clk; + clear_mock(); + sdhci_reg_write(SRS(0x2C), 0xAA55BBCC); + memcpy(&clk, &cm4_mock_emmc[STD_SDHCI_CLK_CTRL], sizeof(clk)); + ck_assert_uint_eq(clk, 0xBBCC); + ck_assert_uint_eq(cm4_mock_emmc[STD_SDHCI_TIMEOUT_CTRL], 0x55); + ck_assert_uint_eq(cm4_mock_emmc[STD_SDHCI_SW_RESET], 0xAA); +} +END_TEST + +/* SRS15 (std 0x3C) write must mask out the unsupported HV4E / A64 bits. */ +START_TEST(test_srs15_masks_hv4e_a64) +{ + uint32_t v; + clear_mock(); + sdhci_reg_write(SRS(STD_SDHCI_HOST_CTRL2), + 0x0000FFFF | SDHCI_SRS15_HV4E | SDHCI_SRS15_A64); + memcpy(&v, &cm4_mock_emmc[STD_SDHCI_HOST_CTRL2], sizeof(v)); + ck_assert_uint_eq(v & (SDHCI_SRS15_HV4E | SDHCI_SRS15_A64), 0); + ck_assert_uint_eq(v & 0xFFFF, 0xFFFF); +} +END_TEST + +/* SRS16 (std 0x40, Capabilities) read must mask out A64S. */ +START_TEST(test_srs16_masks_a64s) +{ + uint32_t caps; + clear_mock(); + caps = 0x12345678 | SDHCI_SRS16_A64S; + memcpy(&cm4_mock_emmc[0x40], &caps, sizeof(caps)); + ck_assert_uint_eq(sdhci_reg_read(SRS(0x40)) & SDHCI_SRS16_A64S, 0); + ck_assert_uint_eq(sdhci_reg_read(SRS(0x40)), caps & ~SDHCI_SRS16_A64S); +} +END_TEST + +/* SRS22 (std 0x58) maps to the legacy SDMA address at std 0x00. */ +START_TEST(test_srs22_maps_to_sdma_addr) +{ + uint32_t v; + clear_mock(); + sdhci_reg_write(SRS(0x58), 0xDEADBEEF); + memcpy(&v, &cm4_mock_emmc[STD_SDHCI_SDMA_ADDR], sizeof(v)); + ck_assert_uint_eq(v, 0xDEADBEEF); + ck_assert_uint_eq(sdhci_reg_read(SRS(0x58)), 0xDEADBEEF); +} +END_TEST + +/* SRS23 (std 0x5C) has no 64-bit addressing: write is a no-op, read is 0. */ +START_TEST(test_srs23_noop) +{ + clear_mock(); + sdhci_reg_write(SRS(0x5C), 0xFFFFFFFF); + ck_assert_uint_eq(sdhci_reg_read(SRS(0x5C)), 0); + /* nothing was written to the window */ + ck_assert_uint_eq(cm4_mock_emmc[0x5C], 0); +} +END_TEST + +/* A plain 32-bit SRS register (e.g. SRS01 std 0x04) round-trips unchanged. */ +START_TEST(test_plain_reg_roundtrip) +{ + uint32_t v; + clear_mock(); + sdhci_reg_write(SRS(0x04), 0xCAFEF00D); + memcpy(&v, &cm4_mock_emmc[0x04], sizeof(v)); + ck_assert_uint_eq(v, 0xCAFEF00D); + ck_assert_uint_eq(sdhci_reg_read(SRS(0x04)), 0xCAFEF00D); +} +END_TEST + +Suite *cm4_sdhci_suite(void) +{ + Suite *s = suite_create("cm4-sdhci"); + TCase *tc = tcase_create("reg_translation"); + + tcase_add_test(tc, test_srs10_byte_decomposition); + tcase_add_test(tc, test_srs11_split); + tcase_add_test(tc, test_srs15_masks_hv4e_a64); + tcase_add_test(tc, test_srs16_masks_a64s); + tcase_add_test(tc, test_srs22_maps_to_sdma_addr); + tcase_add_test(tc, test_srs23_noop); + tcase_add_test(tc, test_plain_reg_roundtrip); + suite_add_tcase(s, tc); + + return s; +} + +int main(void) +{ + int fails; + Suite *s = cm4_sdhci_suite(); + SRunner *sr = srunner_create(s); + + srunner_run_all(sr, CK_NORMAL); + fails = srunner_ntests_failed(sr); + srunner_free(sr); + + return fails; +}