An end-to-end, ultra-low-power hardware accelerated processing pipeline designed to convert continuous-time 1st-order differential equations into a discrete-time integer recurrence matrix. This repository features a bit-true Python simulation framework, a 65nm CMOS architectural silicon compiler, and a fully synthesizable, gate-level Verilog RTL source file.
- Zero-Decimal Optimization: All mathematical operations utilize integer coefficient scaling (Q8 format) to completely eliminate heavy Floating-Point Units (FPUs), minimizing silicon die area and dynamic power consumption.
- Zero-Gate Interconnect Division: Division operators are entirely bypassed using fast bitwise right-shift operators (
>>), implemented as hardwired physical silicon routing traces consuming 0 gate area. - Deterministic Execution: By eliminating conditional software loops, branches, and variable execution states, the unrolled parallel pipeline completes its calculations in perfectly predictable clock cycles.
16 Parallel Inputs ──► [STAGE 1: 16-Channel Parallel Recurrence Bus]│ (Difference Equations / DC Drift Stripping) ──► [STAGE 2: Spatial Transformation Matrix Engine]│ (2x16 Multiplier Array Dot Product) ──► [STAGE 3: Hardwired Bit-Slicing Networks]│ (Zero-Gate Interconnect >> Right Shifts) ──► [Final Output: [X, Y] Trajectory Coordinates]
-
stage1_simulation/linear_matrix_core.py
Status: PASSED ✅ Pure Python bit-true software simulator. Verifies 1st-order linear difference recurrence loops and spatial matrix dimensions using integer-only kinematics over an active time-series timeline. -
stage2_synthesis_estimate/physical_estimator.py
Status: PASSED ✅ 65nm Low-Power CMOS Architectural Gate Compiler. Extracts gate-level resource counts (multipliers, adders, D-flip-flops), calculates total square core area ($µm^2$ ), determines core dimensions, and evaluates thermal power dissipation safety boundaries. -
stage3_hls_compiler/generate_verilog.py
Status: PASSED ✅ MyHDL High-Level Synthesis compilation execution script. Configures the physical hardware pin boundaries, maps parallel vector slices, and compiles the architectural blueprint into Verilog RTL. -
bci_16ch_system.v
Status: PRODUCED 🚀 The final production-ready Verilog RTL source file. Ready for FPGA hardware deployment or industry-standard ASIC physical Place & Route compilers.
| Parameter Layer | Structural Configuration | Functional Role in Silicon Pipeline |
|---|---|---|
| Active Channels | 16 Parallel Sensor Inputs | Captures high-density parallel time-series vector data |
| Sampling Rate | 30,000 Hz (30 kHz) per channel | Standard temporal baseline for high-frequency signal streams |
| Word Length | 16-bit Signed Integers (intbv) |
Keeps quantization noise floor suppressed at 4.40 µV |
| Recurrence Order | 1st-Order Difference Equation | Slashes multiplier footprint in half & minimizes phase lag |
| Decoder Matrix |
|
Transforms high-dimensional parallel data into 2D motion planes |
| Synthesis Standard | Verilog RTL (IEEE 1364) | Ready for industry-standard ASIC Place & Route compilers |
To verify the simulation metrics and re-generate the synthesizable hardware target inside your own workspace:
- Clone this repository and enter the directory:
git clone https://github.com cd Parallel-Difference-Core - Install the hardware definition compiler library:
pip install myhdl
- Run the High-Level Synthesis generator to compile the Python logic into Verilog RTL:
python stage3_hls_compiler/generate_verilog.py
- Run the Architectural Synthesis Compiler to evaluate the physical chip footprint constraints:
python stage2_synthesis_estimate/physical_estimator.py