Synchronous-FIFO

Synchronous FIFO Buffer

A simple and scalable Synchronous First-In, First-Out (FIFO) buffer implemented in Verilog. It handles data buffering inside a single clock domain using a memory array and pointer tracking logic.

Features

• Parameterizable: Easily change the data width and buffer depth.
• Status Flags: Simple logic to detect if the buffer is empty or full.
• Data Protection: Automatically ignores write commands when full and read commands when empty.
• Self-Checking Testbench: Included simulation file checks for errors automatically.

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Signal Interface## Parameters

• WIDTH (Default: 8): The bit-width of each data item.
• DEPTH (Default: 16): The maximum number of items the FIFO can hold (Must be a power of 2).

Ports

Port Name	Direction	Width	Description
clk	Input	1 bit	System clock.
rst	Input	1 bit	Active-low reset (clears the buffer pointers).
wr_en	Input	1 bit	Write enable strobe.
rd_en	Input	1 bit	Read enable strobe.
wr_data	Input	[WIDTH-1:0]	Parallel input data bus.
rd_data	Output	[WIDTH-1:0]	Registered output data bus (updates 1 cycle after read).
empty	Output	1 bit	Active high when the FIFO contains no data.
full	Output	1 bit	Active high when the FIFO is completely filled.

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How to Run the Simulation

You can compile and run the provided testbench using Icarus Verilog (iverilog) and view the waveform with GTKWave:

1. Compile the source and testbench files

iverilog -o fifo_sim fifo.v fifo_tb.v

2. Run the simulation to view output log and generate VCD file

vvp fifo_sim

3. View the timing waveform diagram

gtkwave fifo_tb.vcd

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Design Constraints

1. Power of Two: The DEPTH parameter must always be a power of 2 (e.g., 4, 8, 16, 32) so the internal tracking pointers wrap around correctly.
2. Reset: The rst input is active-low (0 resets the pointers, 1 allows normal operation).