Persistent State Dynamics

What should an internal state do when the world temporarily becomes unobserved?

This project studies deterministic persistent-state dynamics under controlled observation gaps.

A physical FPGA implementation initially used constant-velocity persistence. That model was worse than hold-last-state. The state substrate was then separated from the transition dynamics. Alternative models were evaluated in software, a damped-velocity model was selected on development data, frozen, validated on a locked asset holdout, replicated on a temporally disjoint dataset, and finally mapped back into physical FPGA hardware with exact software/FPGA parity.

This repository contains the public research and evaluation framework. The deployable FPGA bitstream is not distributed.

What is persistent state?

Here, persistent state means an explicit, versioned state estimate that continues to evolve when new observations are unavailable.

When observations are present, the state is corrected using new evidence. When observations are absent, the state can continue evolving according to a frozen transition model rather than simply being reconstructed from scratch at the next inference call.

The state-update clock is conceptually independent of any downstream model inference clock. A consumer can therefore read the current maintained state without being responsible for maintaining that state itself.

This release validates that idea at the level of one deterministic scalar estimator cell.

Research progression

persistent hardware state
        |
constant velocity
        |
falsified vs HOLD
        |
model comparison
        |
damped velocity selected
        |
locked holdout
        |
temporal replication
        |
FPGA mapping
        |
physical replication

The negative constant-velocity result is part of the evidence, not an omitted prototype outcome.

Headline results

Effects are paired differences in native normalized level units. Positive HOLD - model values favor the model.

Experiment	Role	N gaps	HOLD MAE	CV MAE	Damped MAE	Result
Original physical CV	Falsification	512	0.000719604	0.001095287	n/a	CV worse; effect -0.000375683
Locked asset holdout	Confirmatory	512	0.001060367	0.001281819	0.000997750	Damped vs HOLD +0.000062617
Temporal replication	Confirmatory	4,096	0.001879075	0.002371453	0.001826782	+0.000052293; CI [0.000038396, 0.000066069]
Physical damped replication	Physical, qualified	1,024	0.001675271	0.002169138	0.001603566	+0.000071705 vs HOLD; +0.000565573 vs CV; block CI crosses 0

The temporal result used a Q3 2024 one-minute interval across eight assets, with zero observation-row overlap with the prior persistent-dynamics experiments. Positive mean effects occurred in 7/8 assets, 7/8 gap durations, and 3/4 chronological blocks.

The physical run was more heterogeneous: 5/8 assets and 7/8 durations were positive, and the 60-tick gap favored HOLD. The paired gap-bootstrap interval for physical damped versus HOLD was positive, while the shared-start dependence-aware interval crossed zero.

The physical damped model was more clearly separated from the frozen constant-velocity baseline.

The strongest result is not that an FPGA predicts hidden observations better than a CPU. It is that persistent state can be treated as a separable systems layer: transition dynamics can be falsified, selected, independently replicated, and then instantiated in deterministic hardware while preserving the exact frozen state semantics.

Physical implementation

Property	Measured value
Board	Digilent Basys 3
FPGA	Artix-7 XC7A35T-1CPG236C
Clock	100 MHz
Frozen model	DAMPED_VELOCITY_L32768
PREDICT	139 cycles / 1.390 us
CORRECT	141 cycles / 1.410 us
Physical CPU/FPGA parity	34,264 checkpoints / 0 mismatches
Combined host CPU/GPU load change	0 cycles / 0%
Full-board WNS	+0.085 ns
Bitstream SHA256	7ba421869b763787271ee74da6e201cd41c8c4c8b047137e564815176f23c450

The FPGA bitstream is not included in this public repository. Its SHA-256 records the identity of the tested private artifact and is published for provenance only. It is not sufficient for third-party physical reproduction.

Frozen model

At one logical prediction tick:

level_next    = level + old_velocity
velocity_next = old_velocity >>> 1

The level update uses the pre-damped velocity.

The velocity update is an explicitly signed arithmetic right shift. Its equivalence to Q0.16 multiplication by 32768 was tested over 100,011 int32 values, including signed boundaries and positive/negative odd values, with zero mismatches.

The frozen model identity is:

model_id:   DAMPED_VELOCITY_L32768
lambda:     0.5
lambda_q16: 32768
model_hash: 90d32b4b0c4af0385d8af8c08e6cff94f806830c3c1ed880283522c0365768ec

Persistent-state behavior

The physical state distinguishes prediction-only evolution from new observations.

During observation gaps:

PREDICT
  |
  +-- state_version advances
  +-- observation_age increases
  +-- event_sequence does not advance
  +-- state mode becomes PREDICTED
  +-- level and velocity evolve

When a new observation returns:

CORRECT
  |
  +-- measurement is assimilated
  +-- event_sequence advances
  +-- observation_age resets
  +-- innovation is recorded
  +-- state returns to an observed/corrected state

A measured physical sequence matched the frozen software reference at every commit while velocity decayed:

7800 -> 3900 -> 1950 -> 975 -> 487

before the returning observation was assimilated.

Software and hardware identity

The hardware implementation was not tuned after model selection.

The same frozen dynamics were checked through several layers:

research model
      |
fixed-point software adapter
      |
RTL simulation
      |
physical FPGA

Validation included:

• 100,011 signed fixed-point shift-equivalence cases / 0 mismatches
• 72,576 frozen software fixture state rows / 0 mismatches
• 10,000 mixed RTL PREDICT/CORRECT commits / 0 mismatches
• 34,264 physical CPU/FPGA checkpoints / 0 mismatches

This separates model quality from hardware implementation fidelity: the FPGA executes the selected dynamics rather than defining them.

Timing behavior

The physical state engine maintained fixed internal transition latency:

PREDICT: 139 cycles / 1.390 us
CORRECT: 141 cycles / 1.410 us

Across idle, CPU-load, GPU-load, and combined CPU+GPU host conditions, measured internal PREDICT and CORRECT cycle counts did not change.

Host-visible UART/ACK timing is transport and host-scheduling behavior and should not be confused with the internal state-engine latency.

Quick start

python -m venv .venv
. .venv/bin/activate
python -m pip install -e '.[test]'
pytest
python experiments/reproduce_public_fixture.py

The fixture is synthetic and validates software behavior only. Headline result reproduction requires the recorded source described in REPRODUCIBILITY.md.

Public comparison demo

From the repository root, after the quick-start installation, run:

python experiments/run_comparison.py \
    --fixture public \
    --output outputs/public_comparison

This runs HOLD, CV_V3_FROZEN, and DAMPED_VELOCITY_L32768 on the redistributable synthetic fixture. It writes per-gap metrics, per-tick predictions, a gap summary, and four matplotlib figures.

These outputs are synthetic demonstration results; they do not reproduce the headline temporal replication statistics.

Reproducibility levels

This release supports several levels of reproduction.

Software behavior

Anyone can install the package, run the tests, execute the public fixture, and verify the deterministic model/state semantics.

Research-result reproduction

Reproducing the headline statistical results requires the recorded source data or an equivalent reconstruction using the provenance, masks, manifests, seeds, and evaluation procedure documented in REPRODUCIBILITY.md.

Physical evidence

The repository reports the tested board, clock, model identity, timing, physical parity, and bitstream hash.

The deployable FPGA bitstream itself is not distributed, so this release does not claim full third-party physical reproduction of the reported hardware artifact.

Scope

This release tests one scalar estimator cell in a market-data domain at a one-minute cadence.

It does not establish:

• hidden-truth reconstruction
• a general world model
• universal optimality of lambda = 0.5
• calibrated uncertainty
• universal superiority of persistent prediction over HOLD
• general FPGA superiority over CPU systems
• validation of the full multi-entity temporal tensor

The physical damped-vs-HOLD result is qualified by asset heterogeneity, the 60-tick HOLD advantage, and a shared-start dependence-aware confidence interval that crosses zero.

Uncertainty calibration also did not replicate strongly enough to support a general calibration claim.

Read the technical report, claim ledger, and limitations before citing the result.

Next experiment

This release validates one persistent estimator cell.

The next experiment asks whether the same state contract can scale into a persistent temporal tensor across multiple entities, horizons, perceptions, and features.

Conceptually:

current release

one entity
    x
one horizon
    x
one estimator cell
    |
persistent versioned state


next experiment

perception
    x
entity
    x
horizon
    x
feature
    |
persistent temporal state tensor

The planned experiment will test whether multiple cells can independently maintain versioned PREDICT/CORRECT state while preserving deterministic hardware deadlines, and whether downstream learned models benefit from consuming a continuously maintained state rather than reconstructing state from stale or asynchronous observations.

The current work does not claim that the full temporal tensor has already been validated.

See next experiment for the preregistered research direction.

Citation

If you use this repository, please cite the release metadata in CITATION.cff.

License

Licensed under the Apache License, Version 2.0.

The referenced private FPGA bitstream is not distributed as part of this repository.