fix(fpga_diff): clean up XDMA timing constraints#132
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- Split X4 and X8 PCIe lane constraints into complete XDC files. This keeps fpga.xdc free of conditional Tcl and avoids empty lane-port constraints when the selected XDMA width is X4. - Constrain DEBUG_CLK_IN as 25MHz and restore its async group with difftest_pcie_clock. This matches the board debug clock and removes unsafe timing between debug and XDMA stream clocks.
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Split X4 and X8 PCIe lane constraints into complete XDC files. This keeps fpga.xdc free of conditional Tcl and avoids empty lane-port constraints when the selected XDMA width is X4.
Constrain DEBUG_CLK_IN as 25MHz and restore its async group with difftest_pcie_clock. This matches the board debug clock and removes unsafe timing between debug and XDMA stream clocks.