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GLM 5.2: CUDA backend support#517

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GLM 5.2: CUDA backend support#517
giannisanni wants to merge 1 commit into
antirez:glm5.2from
giannisanni:glm52-cuda

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As discussed in #458: CUDA backend support for GLM 5.2, on top of the glm5.2 branch engine.

What it adds

The CUDA implementations of everything the GLM engine needs: MLA attention, DSA indexer, compact KV, routed MoE with IQ2_XXS gate/up/down dp4a kernels, and SSD expert streaming (io_uring O_DIRECT fetch engine with a pread fallback, host LFU expert cache, parallel fetch backfill). The placeholder stubs in ds4_cuda.cu become real implementations; GLM-specific kernels live in ds4_cuda_glm_{kv,indexer,attn,moe,stubs}.inc.

Engine changes (kept minimal)

  • Allow DS4_BACKEND_CUDA through the GLM backend gate.
  • Gate the split value-projection path on the f16 compact cache: it assumes the Metal f16 layout, and on CUDA's f32 compact cache it fails the batch attention-lora encode at layer 0 (this was the only engine-side change needed to make indexed batch prefill work).

Testing

RTX 4060 Ti 16GB (sm_89), 32GB RAM host, Linux, nvcc 12.0, against the official GLM-5.2-UD-IQ2_XXS_RoutedIQ2XXS_blk78Q2K.gguf with --ssd-streaming:

test result
greedy decode, short prompt correct, ~0.3-0.4 t/s
200-token prompt, indexed batch prefill correct retrieval answer, ~3.2 t/s
600-token prompt correct, ~6.5 t/s prefill

Note: this ds4_cuda.cu includes the batch expert-tile LUT initialization fix I also submitted against main as #513 (the tile kernels loaded the IQ2 dequant tables only for n_embd <= 4096; GLM is 7168). Whichever lands first, the other becomes a trivial rebase.

More background on the streaming behavior at these sizes is in #495. Happy to adjust anything to fit the branch's direction.

Implements the CUDA side of GLM 5.2 inference on top of the glm5.2
branch engine: MLA attention, DSA indexer, compact KV, routed MoE with
IQ2_XXS gate/up/down dp4a kernels, and SSD expert streaming (io_uring
O_DIRECT fetch engine, host LFU expert cache, parallel fetch backfill).

Engine changes are minimal:
- allow DS4_BACKEND_CUDA through the GLM backend gate,
- gate the split value-projection path on the f16 compact cache: it
  assumes the Metal f16 layout and fails the batch attention-lora encode
  on CUDA's f32 cache.

The CUDA backend replaces the placeholder stubs with real
implementations and adds the GLM kernel implementations in
ds4_cuda_glm_{kv,indexer,attn,moe,stubs}.inc.

Includes the batch expert-tile LUT initialization fix also submitted
against main as antirez#513 (models with n_embd > 4096).

Tested on RTX 4060 Ti 16GB (sm_89), 32GB RAM host, Linux, against the
official GLM-5.2-UD-IQ2_XXS_RoutedIQ2XXS_blk78Q2K.gguf with
--ssd-streaming: greedy decode correct at ~0.3-0.4 t/s, 200-token batch
prefill correct at ~3.2 t/s, 600-token at ~6.5 t/s.
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