Value circuits new#36
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Since #14 the error locations often pointed to the end of the circuit instead of the correct location. That should now be fixed, along with a regression test.
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RIP Fable.. I find that I typically mix and match accum :: Circuit (Signal dom Int) (Signal dom Int)
accum = circuit \(Fwd (Values i)) -> do
Fwd (Values acc) <- registerC 0 -< Fwd (Values acc')
let acc' = acc + i
idC -< Fwd (Values acc')~ accum :: Circuit (Signal dom Int) (Signal dom Int)
accum = circuit \(Fwd (Values i)) -> do
let
Values acc = register 0 (Values acc')
acc' = acc + i
idC -< Fwd (Values acc')Not sure about any of this, just floating an idea. |
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I'll think about it but adding support in general Haskell expressions and bindings might open a whole can of worms. Right now, since it's limited to the "arrow land", it's relatively simple without much in the way of edge cases (I hope). I'm generally in favour of keeping the plugin simple and predictable at the cost of a bit of verbosity. You can always use helpers (something like |
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Yeah, makes sense. I'd rather have less magic too. |
Value-group logic is lifted to the signal level with `fmap` over a
`bundle` of the group's inputs. Two strictness points there can make
combinational feedback between value groups deadlock simulation:
* `bundle` lifts its first element with `fmap` / `mapSignal#`, which
forces that element's spine. Prepend a lazy unit so no real input
sits in that spine-forcing head slot.
* The logic function matched its inputs strictly, so a constructor
pattern at the boundary (destructuring the sampled value) forced its
input to produce *any* of the group's outputs -- even outputs that do
not use it. That deadlocks when the input depends, through the
circuit, on such an output. Match each value input lazily
(irrefutable), as the bus-level plumbing already does, so an output
only forces the inputs it actually uses.
Both keep value-group feedback well founded without changing the lifted
logic. The library and error-location test suites still pass.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The value level circuit syntax I originally started work on 6 years ago! master...value-circuits
This was written with the anthropic's new fable model. I also got it to add significantly more testing.
This gets you pretty close to being able to write everything with circuit syntax! Mealy machines can be done with a
registerC:It also supports multiple clock domains (although you don't get a great error when you mix them up):
and
DSignalCsupport (makes sure all groups have the same delay):