Randomize proc execution in DSLX Interpreter (PoC)#4522
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Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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This PR introduces experimental changes to the DSLX interpreter, extending it with support for bounded FIFO simulation and randomized proc scheduling to enable validation of different proc execution interleavings.
The PR adds the following options to
interperter_main:simulate_bounded_fifos- enables simulation with bounded FIFOs.seed- initializes the random number generator used to shuffle proc execution order.randomize_proc_execution- enables randomization of proc scheduling.mid_tick_yield- enables mid-tick randomization, effectively allowing randomization at all I/O points. (This option is intended for demonstration purposes only)This PR also provides examples in the
examples/interpreter_pocdirectory, together with a README describing their purpose and usage.