openmv · kwagyeman · Mar 29, 2026 · Mar 29, 2026 · Mar 29, 2026 · Apr 4, 2026
diff --git a/docs/mimxrt/pinout.rst b/docs/mimxrt/pinout.rst
@@ -477,3 +477,34 @@ assignment to the Encoder or Counter are:
 
   Pins J3_14, J3_15, J4_19, J4_20, J5_15, J5_16, J5_17, J5_22, J5_23, J5_24, J5_25 and J5_26.
   Pins J3_14 and J3_15 cannot be used for the match output.
+
+
+.. _mimxrt_can_pinout:
+
+|
+|
+
+Hardware CAN pin assignment
+---------------------------
+
+Pin assignments for a few MIMXRT boards. The list show the MCU TX/RX pins.
+
+=================  ===========  ===========  =======
+Board              CAN1         CAN2         CAN3
+=================  ===========  ===========  =======
+Teensy 4.0         A8/A9        D1/D0        -
+Teensy 4.1         A8/A9        D1/D0        D31/D30
+Seeed Arch MIX     J4_08/J4_09  J3_14/J3_15
+MIMXRT1020_DEV     Transceiver  -            -
+MIMXRT1050_DEV     Transceiver  -            -
+MIMXRT1060_DEV     Transceiver  -            -
+MIMXRT1064_DEV     Transceiver  -            -
+MIMXRT1170_DEV     Transceiver  D4/D8        -
+phyBOARD-RT1170    CAN port     -            -
+=================  ===========  ===========  =======
+
+All supported MIMXRT Developments boards are equipped with a CAN transceiver
+and do expose it's MCU pins. At the 3 pin transceiver connector
+CAN_H is as pin 1, CAN_L at Pin 3. Pin 2 is connected to GND.
+A documentation showing the CAN pin assignments of the phyBOARD-RT1170
+does not seem to be accessible.
diff --git a/extmod/machine_can.c b/extmod/machine_can.c
@@ -272,6 +272,7 @@ static void machine_can_init_helper(machine_can_obj_t *self, size_t n_args, cons
     int brp = calculate_brp(bitrate_nom, f_clock, &tseg1, &tseg2, sample_point, false);
 
     // Set up the hardware
+    self->bitrate = bitrate_nom;
     self->tseg1 = tseg1;
     self->tseg2 = tseg2;
     self->brp = brp;
@@ -567,6 +568,7 @@ static mp_obj_t machine_can_set_filters(mp_obj_t self_in, mp_obj_t filters) {
                 );
         }
     }
+    machine_can_port_set_filter_done(self);
 
     return mp_const_none;
 }

diff --git a/extmod/machine_can_port.h b/extmod/machine_can_port.h
@@ -92,7 +92,7 @@ typedef struct {
 typedef struct _machine_can_obj_t {
     mp_obj_base_t base;
     mp_uint_t can_idx;
-
+    uint32_t bitrate;
     // Timing register settings
     byte tseg1;
     byte tseg2;
@@ -154,6 +154,9 @@ static mp_uint_t machine_can_port_max_data_len(mp_uint_t flags);
 // CAN_MSG_FLAG_EXT_ID bit in 'flags' differentiates the type).
 static void machine_can_port_set_filter(machine_can_obj_t *self, int filter_idx, mp_uint_t can_id, mp_uint_t mask, mp_uint_t flags);
 
+// Report that the set of filters is complete for now.
+static void machine_can_port_set_filter_done(machine_can_obj_t *self);
+
 // Update interrupt configuration based on the new contents of 'self'
 static void machine_can_update_irqs(machine_can_obj_t *self);
 

diff --git a/ports/mimxrt/Makefile b/ports/mimxrt/Makefile
@@ -185,6 +185,10 @@ endif
 ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064 MIMXRT1176))
 SRC_HAL_IMX_C += $(MCUX_SDK_DIR)/drivers/usdhc/fsl_usdhc.c
 INC_HAL_IMX += -I$(TOP)/$(MCUX_SDK_DIR)/drivers/usdhc
+
+SRC_HAL_IMX_C += $(MCUX_SDK_DIR)/drivers/flexcan/fsl_flexcan.c
+INC_HAL_IMX += -I$(TOP)/$(MCUX_SDK_DIR)/drivers/flexcan
+MICROPY_PY_MACHINE_CAN = 1
 endif
 
 ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1015 MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064 MIMXRT1176))
@@ -413,6 +417,7 @@ endif
 # Set default values for optional variables
 MICROPY_HW_SDRAM_AVAIL ?= 0
 MICROPY_HW_SDRAM_SIZE ?= 0
+MICROPY_PY_MACHINE_CAN ?= 0
 
 # Configure default compiler flags
 CFLAGS += \
@@ -434,6 +439,7 @@ CFLAGS += \
 	-DMICROPY_HW_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \
 	-DMICROPY_HW_SDRAM_AVAIL=$(MICROPY_HW_SDRAM_AVAIL) \
 	-DMICROPY_HW_SDRAM_SIZE=$(MICROPY_HW_SDRAM_SIZE) \
+	-DMICROPY_PY_MACHINE_CAN=$(MICROPY_PY_MACHINE_CAN) \
 	-DXIP_BOOT_HEADER_ENABLE=1 \
 	-DXIP_EXTERNAL_FLASH=1 \
 	-fdata-sections \

diff --git a/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h
@@ -77,6 +77,14 @@
     { 0 }, { 0 }, \
     { IOMUXC_GPIO_SD_B1_02_LPI2C4_SCL }, { IOMUXC_GPIO_SD_B1_03_LPI2C4_SDA },
 
+#define MICROPY_HW_CAN1_NAME "CAN1"
+#define MICROPY_HW_NUM_CAN (1)
+#define MICROPY_HW_CAN_INDEX { 1 }
+#define MICROPY_HW_NUM_CAN_IRQS (1)
+
+#define IOMUX_TABLE_CAN \
+    { IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX }, { IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX },
+
 #define MICROPY_PY_MACHINE_I2S (1)
 #define MICROPY_HW_I2S_NUM (1)
 #define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux }

diff --git a/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h
@@ -65,6 +65,15 @@
     { 0 }, { 0 }, \
     { IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL }, { IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA },
 
+#define MICROPY_HW_CAN1_NAME "CAN1"
+#define MICROPY_HW_NUM_CAN (1)
+#define MICROPY_HW_CAN_INDEX { 2 }
+#define MICROPY_HW_NUM_CAN_IRQS (1)
+
+#define IOMUX_TABLE_CAN \
+    { 0 }, { 0 }, \
+    { IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX }, { IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX },
+
 #define MICROPY_PY_MACHINE_I2S (1)
 #define MICROPY_HW_I2S_NUM (1)
 #define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux }

diff --git a/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h
@@ -65,6 +65,15 @@
     { 0 }, { 0 }, \
     { IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL }, { IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA },
 
+#define MICROPY_HW_CAN1_NAME "CAN1"
+#define MICROPY_HW_NUM_CAN (1)
+#define MICROPY_HW_CAN_INDEX { 2 }
+#define MICROPY_HW_NUM_CAN_IRQS (1)
+
+#define IOMUX_TABLE_CAN \
+    { 0 }, { 0 }, \
+    { IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX }, { IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX },
+
 #define MICROPY_PY_MACHINE_I2S (1)
 #define MICROPY_HW_I2S_NUM (1)
 #define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux }

diff --git a/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h
@@ -65,6 +65,15 @@
     { 0 }, { 0 }, \
     { IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL }, { IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA },
 
+#define MICROPY_HW_CAN1_NAME "CAN1"
+#define MICROPY_HW_NUM_CAN (1)
+#define MICROPY_HW_CAN_INDEX { 2 }
+#define MICROPY_HW_NUM_CAN_IRQS (1)
+
+#define IOMUX_TABLE_CAN \
+    { 0 }, { 0 }, \
+    { IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX }, { IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX },
+
 #define MICROPY_PY_MACHINE_I2S (1)
 #define MICROPY_HW_I2S_NUM (1)
 #define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux }

diff --git a/ports/mimxrt/boards/MIMXRT1170_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1170_EVK/mpconfigboard.h
@@ -103,6 +103,17 @@
     { IOMUXC_GPIO_LPSR_05_LPI2C5_SCL }, { IOMUXC_GPIO_LPSR_04_LPI2C5_SDA }, \
     { IOMUXC_GPIO_LPSR_11_LPI2C6_SCL }, { IOMUXC_GPIO_LPSR_10_LPI2C6_SDA },
 
+#define MICROPY_HW_CAN1_NAME "CAN1"
+#define MICROPY_HW_CAN2_NAME "CAN2"
+#define MICROPY_HW_NUM_CAN (2)
+#define MICROPY_HW_CAN_INDEX { 3, 1 }
+#define MICROPY_HW_NUM_CAN_IRQS (2)
+
+#define IOMUX_TABLE_CAN \
+    { IOMUXC_GPIO_AD_06_FLEXCAN1_TX }, { IOMUXC_GPIO_AD_07_FLEXCAN1_RX }, \
+    { 0 }, { 0 }, \
+    { IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX }, { IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX },
+
 #define MICROPY_PY_MACHINE_I2S (1)
 #define MICROPY_HW_I2S_NUM (1)
 #define I2S_CLOCK_MUX { 0, kCLOCK_Root_Sai1, kCLOCK_Root_Sai2, kCLOCK_Root_Sai3, kCLOCK_Root_Sai4 }

diff --git a/ports/mimxrt/boards/OPENMV_RT1060/mpconfigboard.h b/ports/mimxrt/boards/OPENMV_RT1060/mpconfigboard.h
@@ -156,6 +156,8 @@ extern void mimxrt_hal_bootloader(void);
 // Bus      HW-CAN       Logical CAN
 // External FLEXCAN2 ->  0
 
+#define MICROPY_HW_CAN1_NAME "CAN1"
+#define MICROPY_HW_NUM_CAN (1)
 #define MICROPY_HW_CAN_INDEX { 2 }
 #define MICROPY_HW_NUM_CAN_IRQS (1)
 

diff --git a/ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.h b/ports/mimxrt/boards/PHYBOARD_RT1170/mpconfigboard.h
@@ -107,6 +107,16 @@
     { IOMUXC_GPIO_LPSR_08_LPI2C5_SDA }, { IOMUXC_GPIO_LPSR_09_LPI2C5_SCL }, \
     { 0 }, { 0 },
 
+#define MICROPY_HW_CAN1_NAME "CAN1"
+#define MICROPY_HW_NUM_CAN (1)
+#define MICROPY_HW_CAN_INDEX { 3 }
+#define MICROPY_HW_NUM_CAN_IRQS (1)
+
+#define IOMUX_TABLE_CAN \
+    { 0 }, { 0 }, \
+    { 0 }, { 0 }, \
+    { IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX }, { IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX },
+
 #define MICROPY_PY_MACHINE_I2S (1)
 #define MICROPY_HW_I2S_NUM (1)
 #define I2S_CLOCK_MUX { 0, kCLOCK_Root_Sai1, kCLOCK_Root_Sai2, kCLOCK_Root_Sai3, kCLOCK_Root_Sai4 }

diff --git a/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h b/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h
@@ -77,6 +77,15 @@
     { IOMUXC_GPIO_B0_04_LPI2C2_SCL }, { IOMUXC_GPIO_B0_05_LPI2C2_SDA }, \
     { IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL }, { IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA }
 
+#define MICROPY_HW_CAN1_NAME "CAN1"
+#define MICROPY_HW_NUM_CAN (2)
+#define MICROPY_HW_CAN_INDEX { 1, 2 }
+#define MICROPY_HW_NUM_CAN_IRQS (2)
+
+#define IOMUX_TABLE_CAN \
+    { IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX }, { IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX }, \
+    { IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX }, { IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX },
+
 #define MICROPY_PY_MACHINE_I2S (1)
 #define MICROPY_HW_I2S_NUM (1)
 #define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux }

diff --git a/ports/mimxrt/boards/TEENSY40/mpconfigboard.h b/ports/mimxrt/boards/TEENSY40/mpconfigboard.h
@@ -68,6 +68,16 @@
     { IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL }, { IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA }, \
     { IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL }, { IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA },
 
+#define MICROPY_HW_CAN1_NAME "CAN1"
+#define MICROPY_HW_CAN2_NAME "CAN2"
+#define MICROPY_HW_NUM_CAN (2)
+#define MICROPY_HW_CAN_INDEX { 1, 2 }
+#define MICROPY_HW_NUM_CAN_IRQS (2)
+
+#define IOMUX_TABLE_CAN \
+    { IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX }, { IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX }, \
+    { IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX }, { IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX },
+
 #define MICROPY_PY_MACHINE_I2S (1)
 #define MICROPY_HW_I2S_NUM (2)
 #define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux }

diff --git a/ports/mimxrt/boards/TEENSY41/mpconfigboard.h b/ports/mimxrt/boards/TEENSY41/mpconfigboard.h
@@ -70,6 +70,18 @@
     { IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL }, { IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA }, \
     { IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL }, { IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA },
 
+#define MICROPY_HW_CAN1_NAME "CAN1"
+#define MICROPY_HW_CAN2_NAME "CAN2"
+#define MICROPY_HW_CAN3_NAME "CAN3"
+#define MICROPY_HW_NUM_CAN (3)
+#define MICROPY_HW_CAN_INDEX { 1, 2, 3 }
+#define MICROPY_HW_NUM_CAN_IRQS (3)
+
+#define IOMUX_TABLE_CAN \
+    { IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX }, { IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX }, \
+    { IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX }, { IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX }, \
+    { IOMUXC_GPIO_EMC_36_FLEXCAN3_TX }, { IOMUXC_GPIO_EMC_37_FLEXCAN3_RX },
+
 #define MICROPY_PY_MACHINE_I2S (1)
 #define MICROPY_HW_I2S_NUM (2)
 #define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux }