Cache-line false sharing linter for Rust structs
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May 25, 2026 - Rust
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mesi
Here are 9 public repositories matching this topic...
An in-depth project focusing on the design and simulation of a split L1 cache in C++. This repository covers MESI protocol operations, comprehensive test cases, and simulation results, showcasing strategies for enhancing cache coherence and performance. This is a class project from ECE 585: Microprocessor System Design at Portland State University
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Mar 23, 2024 - C++
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Nov 30, 2018 - C
Simulador de coherencia Cache de un procesador Multinucleo: protocolo MESI - 1 cache por Nucleo - Universidad Nacional Patagónica San Juan Bosco - OPEN SOURCE
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Aug 3, 2023 - JavaScript
A C++ simulator for a 32-bit split-L1 cache (separate I/D) with MESI coherence, pseudo-LRU replacement, and write-back/write-allocate policy — reads a trace and reports hit/miss statistics or per-operation L2 bus messages.
cpp cpu-cache computer-architecture cache-simulator memory-hierarchy mesi cache-coherence write-back pseudo-lru
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Jul 4, 2026 - C++
Introduction to cache coherence: false sharing, MESI protocol and vectorization
processor-architecture workshop simd jmh simd-programming vectorization workshop-materials simd-instructions cache-invalidation jmh-benchmarks writeback mesi cache-line cache-coherence multi-core-architectures false-sharing cache-line-padding mesi-protocol writethrough cache-coherency
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Nov 16, 2024 - Java
A C++ concurrency learning repository with implementations of various synchronization primitives and concurrent data structures.
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Nov 1, 2025 - C++
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